Anyone tried to use DC to generate netlist for FPGA?

[tony_taoyh]

netlist license fpga

HI, I think there are two methods:

(1) First use DC and one normal ASIC library,
then transform the generated netlist using some
function equivalent transform.

(2) According to the rule of Library Compiler,
make one library (*.db) for the FPGA cell.
Then DC can use the library.


Aftre (1) or (2) the netlist is dumped into FPGA Compiler
for furthur optimization.


The target is to utilize the powerful function of DC for optimization.

Is it possible?

No money to pay for "DC FPGA"....

 

[FLEXcertifydll]

dc fpga library

I think your means DC for FPGA synthesis, but it's not a good choice.

1. DC is for stand cell design, not for programable logic design. That is to say the compile library is entirely different. You know the ASIC based on the 2 input NAND, but FPGA based on vendor's device model.

2.If you want to use some ASIC IP under DC in FPGA domain, one way is EDIF file. you can transform them into edif netlist, then load into FPGA synthesis tool, run FPGA flow.

 

[tony_taoyh]

This morning, I download the Xinlix Library from this website:
**broken link removed**

And tried to use DC synthesize one small block,
it can work.

From the log file:
dc_shell> Information: Checking out the license 'DesignWare'. (SEC-104)
Information: Evaluating DesignWare library utilization. (UISN-27)

============================================================================
| DesignWare Building Block Library | Version | Available |
============================================================================
| Basic DW Building Blocks | V-2004.06-DWF_0406 | * |
| Licensed DW Building Blocks | V-2004.06-DWF_0406 | * |
| xdw_virtex | 0.20 BETA | * |
============================================================================

Anyone have idea for this?

Thanks a lot.