Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Basically, PLL synthesises some frequency which means there is an oscillator in it - VCO. You lock the frequency and phase of this oscillator to the external to the PLL reference frequency.
In DLL there is no VCO, just a delay line. And consequently the DLL does not generate frequency (although there are articles about DLLs used to synthesize clock). DLL just delays the external reference clock and by doing this it locks its output phase to that of the reference.
The DLL loop is simpler to compensate, it is usually first order, while PLL feedback loop is higher order - second, but in reality third order, and you'll have to be careful compensating it. Because PLL incorporates an oscillator it is more prone to jitter, generated inside the loop. DLL is better in this respect because it will just repeat the jitter fo the input signal and perhaps add something from the elements of the delay line.
DLL stand for Delay Lock Loop
PLL stand for Phase Lock Loop
The main different between DLL and PLL is DLL use delay control logic instead of Voltage Controlled Oscillator (VCO). The advantages of DLL is provide Better jitter performance, stability and simple design. However, since the limited phase capture range of DLL, it is no change in frequency. For PLL, it is very suitable for clock synthesis, but it cause high jitter due to phase noise accumulation.
For the purpose of multiplying clock frequency you better use PLL (dividing frequency you can do with a counter, no need for PLL). I have heard that people try to use DLLs also for multiplying but I don't have any article titles in my mind right now and don't have experience with this application of DLLs. Look for IEEE articles on this, you should find. But I think PLL approach is more straight-forward in this respect.
VCO needs some control voltage (or current) which will set its oscillation frequency and phase to the value needed to lock with the input frequency to the PLL. Charge pump is the block that sets this voltage (or current through a voltage to current convertor). The idea behind a charge pump is to have a capacitor and two currents, one pumping charge into the capacitor thus increasing the voltage accross it, the other current removing the charge from it and reducing the voltage. These are switched currents - when the phase difference between the input of the PLL and the output of the VCO has a certain sign you switch on one of these two currents. When the phase difference is with the oposite sign - switch off the first current and switch on the other one. In this way the direction the voltage across the capacitor changes reflects the phase difference. If there is no phase difference both currents are switched off. There can be instants when both currents are on, but since they are nominally the same, no net current should charge or discharge the capacitor.
This said, there are a lot of non-idealities that make the function of the chrge pump depart from the described operation, which causes different effect in the operation of the PLL itself.
By the way, charge pump can also be used to control the delay of a DLL.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.