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Anybody has some experiences with Xilinx Forge compiler?

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Xilinx's Forge is a behavioral compiler that can generate RTL verilog code from Java byte code,
which can be implemented in a Xilinx FPGA.

**broken link removed**
 

Here are some PDF files about Xilinx Forge compiler.
 

That sounds very good, has anyone here used it? please give some comments on the compiler.

eman
 

Celoxica DK1.1 also does the similar job but using Handel-C code !
 

JHDL is another academic tool
that can synthesize an FPGA netlist from Java bytecode.
 

Forge

Hi,

does anyone have any docu about forge ... which java expression
need to b used to generate special HW segments ... the docu
with forge from X@l@nx is not so much ... Thankx

heat
 

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