Why are you so much worried about the version/setup procedure? any installation procedure in linux is easy if you know what u r doing & can become sketchy if u don't know. Anyway, the best thing for u is to install 'wine' first & then u can easily install the windows version of xilinx in ubuntu..Xilinx? To my awareness, I did not know that xilinx can be installed on ubuntu natty narwhal 11.04. But anyway that is news to me. Which version of xilinx are you talking about? And is the installation procedure sketchy (like that of modelsim) or straightforward? ---------- Post added 29-06-11 at 00:39 ---------- Previous post was 28-06-11 at 23:48 ---------- ---------- Post added at 00:40 ---------- Previous post was at 00:39 ---------- hi Deepon, can you elaborate on what you said? Like the version of xilinx which works under ubntu 11.04?
Edit: Well, I didnt notice that you had mentioned me to install the windows version of xilinx on ubuntu. Thanks for mentioning that. But I would like to ask you if all the features of xilinx ise are fully functional in ubuntu 11.04 natty narwhal through the wine emulator such as the logic synthesis, schematic generation, place and route, bit file generation etc? ??
Why I am asking this is because I googled to find that different ppl complain about different compatibility issues with xilinx on linux.. So I want to know to what extent the xilinx is operational in this setup of ubuntu. I am hoping you are also using the same version of linux ubuntu as me. :grin:
@elSilviu,
Thanks I will download the xilinx ise 13.1 from the xilinx website and follow the instructions for the linux installation. I only hope it works under ubuntu. I am sure that it works under redhat. But as with ubuntu always fingers crossed. !
$ cat tb.sh
#!/bin/sh
PUNISIM=''
WORK_DIR="work"
STOP_TIME="100ns"
while getopts 'p:s:u:w:' OPTION
do
case $OPTION in
p) PROJECT="$OPTARG"
;;
s) STOP_TIME="$OPTARG"
;;
u) PUNISIM="-P$OPTARG"
;;
w) WORK_DIR="$OPTARG"
esac
done
shift $(($OPTIND -1 ))
mkdir $WORK_DIR 2> /dev/null
echo "Importing vhd Files"
ghdl -i --ieee=synopsys $PUNISIM --workdir=$WORK_DIR src/*.vhd
echo "Compiling"
ghdl -m --ieee=synopsys $PUNISIM --workdir=$WORK_DIR $PROJECT
echo "Running"
mv $PROJECT $WORK_DIR/
work/$PROJECT --stop-time=$STOP_TIME --vcd=$WORK_DIR/$PROJECT.vcd
echo "Show wave forms"
gtkwave $WORK_DIR/$PROJECT.vcd $WORK_DIR/$PROJECT.trace
$ cat make_project.sh
#!/bin/sh
while getopts 'p:t:u:' OPTION
do
case $OPTION in
p) PROJECT="$OPTARG"
;;
t) TOP_LEVEL="$OPTARG"
;;
u) UCF_FILE="$OPTARG"
esac
done
shift $(($OPTIND - 1))
./syntesis.sh -p $PROJECT
./map.sh -p $PROJECT -t $TOP_LEVEL -u $UCF_FILE
./par.sh -t $TOP_LEVEL
./bitgen.sh -p $PROJECT -t $TOP_LEVEL
$ cat syntesis.sh
#!/bin/sh
while getopts 'p:' OPTION
do
case $OPTION in
p) PROJECT="$OPTARG"
esac
done
shift $(($OPTIND -1 ))
$XILINX/bin/lin/xst -intstyle ise -ifn $PROJECT.xst -ofn $PROJECT.syr
$ cat map.sh
#!/bin/sh
while getopts 'p:t:u:' OPTION
do
case $OPTION in
p) PROJECT="$OPTARG"
;;
t) TOP_LEVEL="$OPTARG"
;;
u) UCF_FILE="$OPTARG"
esac
done
shift $(($OPTIND - 1))
echo "ngbuild"
$XILINX/bin/lin/ngdbuild $PROJECT $TOP_LEVEL -uc $UCF_FILE
echo "map"
$XILINX/bin/lin/map -o map.ncd $TOP_LEVEL
$ cat par.sh
#!/bin/sh
while getopts 't:' OPTION
do
case $OPTION in
t) TOP_LEVEL="$OPTARG"
esac
done
shift $(($OPTIND - 1))
$XILINX/bin/lin/par -w -ol high map.ncd $TOP_LEVEL.ncd
$ cat bitgen.sh
#!/bin/sh
#!/bin/sh
while getopts 'p:t:' OPTION
do
case $OPTION in
p) PROJECT="$OPTARG"
;;
t) TOP_LEVEL="$OPTARG"
esac
done
shift $(($OPTIND - 1))
$XILINX/bin/lin/bitgen -g startupclk:Cclk -w $TOP_LEVEL $PROJECT.bit
$ cat LED.xst
set -tmpdir "tmp"
set -xsthdpdir "xst"
run
-ifn LED.prjise
-ifmt mixed
-ofn LED
-ofmt NGC
-p xc3s500e-4-fg320
-top frec_div
-opt_mode Speed
-opt_level 1
-iuc NO
-keep_hierarchy NO
-netlist_hierarchy as_optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-mult_style auto
-iobuf YES
-max_fanout 500
-bufg 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Yes
-use_sync_set Yes
-use_sync_reset Yes
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
$ cat LED.prjise
vhdl work "../src/frec_div.vhd"
$ iverilog -v
Icarus Verilog version 0.8.6 ($Name: $)
Copyright 1998-2003 Stephen Williams
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
iverilog: No input files.
Usage: iverilog [-ESvV] [-B base] [-c cmdfile] [-g1|-g2|-g3.0]
[-D macro[=defn]] [-I includedir] [-M depfile] [-m module]
[-N file] [-o filename] [-p flag=value]
[-s topmodule] [-t target] [-T min|typ|max]
[-W class] [-y dir] [-Y suf] source_file(s)
See man page for details.
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We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?