# any synthesis tool for linux ubuntu 11.04 natty narwhal?

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#### srinpraveen

##### Member level 2
Hi ppl..
Is there any good synthesis tool for ubuntu 11.04 natty narwhal? I have been using ver 0.9 of lcarus iverilog simulator. But unfortunately it does not support synthesis while the previous version of it does. I can't roll back to the previous version of it as the synaptic package manager does not allow me to do so. So does anyone know of a good synthesis tool for linux ubuntu? Also I desperately tried to get modelsim working in ubuntu 11.04 through wine.

But I am not sure how to install it. I am not able to run a file called install.linux.

Can anyone help me on my problems? Thanks.

#### Deepon

##### Member level 1
You can use Xilinx...

#### srinpraveen

##### Member level 2
Xilinx? To my awareness, I did not know that xilinx can be installed on ubuntu natty narwhal 11.04. But anyway that is news to me. Which version of xilinx are you talking about? And is the installation procedure sketchy (like that of modelsim) or straightforward?

---------- Post added 29-06-11 at 00:39 ---------- Previous post was 28-06-11 at 23:48 ----------

---------- Post added at 00:40 ---------- Previous post was at 00:39 ----------

hi Deepon, can you elaborate on what you said? Like the version of xilinx which works under ubntu 11.04?

#### Deepon

##### Member level 1
Xilinx? To my awareness, I did not know that xilinx can be installed on ubuntu natty narwhal 11.04. But anyway that is news to me. Which version of xilinx are you talking about? And is the installation procedure sketchy (like that of modelsim) or straightforward? ---------- Post added 29-06-11 at 00:39 ---------- Previous post was 28-06-11 at 23:48 ---------- ---------- Post added at 00:40 ---------- Previous post was at 00:39 ---------- hi Deepon, can you elaborate on what you said? Like the version of xilinx which works under ubntu 11.04?
Why are you so much worried about the version/setup procedure? any installation procedure in linux is easy if you know what u r doing & can become sketchy if u don't know. Anyway, the best thing for u is to install 'wine' first & then u can easily install the windows version of xilinx in ubuntu..

#### srinpraveen

##### Member level 2
Hi Deepon, I am a newbie to ubuntu and in general linux. I have been only a windows user so far. But I have been getting better in ubuntu day by day. And yes I already have wine installed. I would like to know which version of xilinx you have in your system so that should any doubts arise, I can discuss that over here. I feel that will be better than me installing a version of xilinx and maybe getting stuck in the middle considering I am in the infant stage of the learning curve of linux ubuntu.

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#### srinpraveen

##### Member level 2
Edit: Well, I didnt notice that you had mentioned me to install the windows version of xilinx on ubuntu. Thanks for mentioning that. But I would like to ask you if all the features of xilinx ise are fully functional in ubuntu 11.04 natty narwhal through the wine emulator such as the logic synthesis, schematic generation, place and route, bit file generation etc? ??

Why I am asking this is because I googled to find that different ppl complain about different compatibility issues with xilinx on linux.. So I want to know to what extent the xilinx is operational in this setup of ubuntu. I am hoping you are also using the same version of linux ubuntu as me. :grin:

#### eSilviu

##### Newbie level 6
Edit: Well, I didnt notice that you had mentioned me to install the windows version of xilinx on ubuntu. Thanks for mentioning that. But I would like to ask you if all the features of xilinx ise are fully functional in ubuntu 11.04 natty narwhal through the wine emulator such as the logic synthesis, schematic generation, place and route, bit file generation etc? ??

Why I am asking this is because I googled to find that different ppl complain about different compatibility issues with xilinx on linux.. So I want to know to what extent the xilinx is operational in this setup of ubuntu. I am hoping you are also using the same version of linux ubuntu as me. :grin:

From the xilinx website, you can download a linux version of their software. It installs and runs exactly like the windows version. It's even possible to use some USB to Jtag burners to burn the FPGAs.
so try-it!

#### srinpraveen

##### Member level 2
@elSilviu,
Thanks I will download the xilinx ise 13.1 from the xilinx website and follow the instructions for the linux installation. I only hope it works under ubuntu. I am sure that it works under redhat. But as with ubuntu always fingers crossed. !

#### eSilviu

##### Newbie level 6
@elSilviu,
Thanks I will download the xilinx ise 13.1 from the xilinx website and follow the instructions for the linux installation. I only hope it works under ubuntu. I am sure that it works under redhat. But as with ubuntu always fingers crossed. !

I use-it under Ubuntu to "play" with a Digilent Basys2 board. So it should work properly.

srinpraveen

### srinpraveen

Points: 2

#### srinpraveen

##### Member level 2
thanks for the info buddy..I will just follow the linux instructions in the manual and go ahead..I am currently downloading the xilinx ise design suite from the xilinx site. I will revert back in case i have some problems. The ise suite from the site is free only right? It says ISE webpack is free. Which means the part of the software suite that we use for verilog code writing, simulation, waveform viewing, synthesis and schematic procurement is also free right?

#### srinpraveen

##### Member level 2
@eSilviu
I installed the xilinx ise as per the instructions in the manual. I was able to run ise. But I tried to check if a sample program can be compiled. Its a simple counter. The compile was not successful. It threw some weird error saying "/opt/Xilinx/13.1/ISE_DS/ISE/bin/lin64/unwrapped/xst: symbol lookup error: /opt/Xilinx/13.1/ISE_DS/ISE//lib/lin64/libCs.so: undefined symbol: _ZN9Xdm_Event9TrackableD2Ev
Process "Check Syntax" failed".
I googled this error to check if its solvable. There are a few links in the xilinx forum which point out to the fact that the ise 13.1 webpack is still not fully compatible with ubuntu 11.04 natty narwhal. It seems there is some memory issue related to how ISE was designed. So that's really shocking.

By the way, which version of ubuntu are you using? How is it that its workng for you? Is it a lower version of ubuntu that you are using probably 10.04 or something?

#### aarmalo

##### Junior Member level 1
If want a stable enviroment to work, you need to install LTS version, I have ISE (10.x and 12.x) in Ubuntu 10.04 and works well, but I have time that I don't use ISE because have my own scripts to simulate (with ghdl) and synthesis.

Code:
$cat tb.sh #!/bin/sh PUNISIM='' WORK_DIR="work" STOP_TIME="100ns" while getopts 'p:s:u:w:' OPTION do case$OPTION in
p) PROJECT="$OPTARG" ;; s) STOP_TIME="$OPTARG"
;;
u) PUNISIM="-P$OPTARG" ;; w) WORK_DIR="$OPTARG"
esac
done
shift $(($OPTIND -1 ))

mkdir $WORK_DIR 2> /dev/null echo "Importing vhd Files" ghdl -i --ieee=synopsys$PUNISIM --workdir=$WORK_DIR src/*.vhd echo "Compiling" ghdl -m --ieee=synopsys$PUNISIM --workdir=$WORK_DIR$PROJECT
echo "Running"
mv $PROJECT$WORK_DIR/
work/$PROJECT --stop-time=$STOP_TIME --vcd=$WORK_DIR/$PROJECT.vcd
echo "Show wave forms"
gtkwave $WORK_DIR/$PROJECT.vcd $WORK_DIR/$PROJECT.trace

For velilog exist icarus verilog (https://iverilog.icarus.com/):
---> Icarus Verilog is a Verilog simulation and synthesis tool

For synthesis:
Code:
$cat make_project.sh #!/bin/sh while getopts 'p:t:u:' OPTION do case$OPTION in
p) PROJECT="$OPTARG" ;; t) TOP_LEVEL="$OPTARG"
;;
u) UCF_FILE="$OPTARG" esac done shift$(($OPTIND - 1)) ./syntesis.sh -p$PROJECT
./map.sh -p $PROJECT -t$TOP_LEVEL -u $UCF_FILE ./par.sh -t$TOP_LEVEL
./bitgen.sh -p $PROJECT -t$TOP_LEVEL

Code:
$cat syntesis.sh #!/bin/sh while getopts 'p:' OPTION do case$OPTION in
p) PROJECT="$OPTARG" esac done shift$(($OPTIND -1 ))$XILINX/bin/lin/xst -intstyle ise -ifn $PROJECT.xst -ofn$PROJECT.syr

Code:
$cat map.sh #!/bin/sh while getopts 'p:t:u:' OPTION do case$OPTION in
p) PROJECT="$OPTARG" ;; t) TOP_LEVEL="$OPTARG"
;;
u) UCF_FILE="$OPTARG" esac done shift$(($OPTIND - 1)) echo "ngbuild"$XILINX/bin/lin/ngdbuild $PROJECT$TOP_LEVEL -uc $UCF_FILE echo "map"$XILINX/bin/lin/map -o map.ncd $TOP_LEVEL Code: $ cat par.sh
#!/bin/sh
while getopts 't:' OPTION
do
case $OPTION in t) TOP_LEVEL="$OPTARG"
esac
done
shift $(($OPTIND - 1))

$XILINX/bin/lin/par -w -ol high map.ncd$TOP_LEVEL.ncd

Code:
$cat bitgen.sh #!/bin/sh #!/bin/sh while getopts 'p:t:' OPTION do case$OPTION in
p) PROJECT="$OPTARG" ;; t) TOP_LEVEL="$OPTARG"

esac
done
shift $(($OPTIND - 1))

$XILINX/bin/lin/bitgen -g startupclk:Cclk -w$TOP_LEVEL $PROJECT.bit The only you need to write is the xst file and prjise, but from any previous project can learn how to make them. ex. Code: $ cat LED.xst
set -tmpdir "tmp"
set -xsthdpdir "xst"
run
-ifn LED.prjise
-ifmt mixed
-ofn LED
-ofmt NGC
-p xc3s500e-4-fg320
-top frec_div
-opt_mode Speed
-opt_level 1
-iuc NO
-keep_hierarchy NO
-netlist_hierarchy as_optimized
-rtlview Yes
-glob_opt AllClockNets
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-mult_style auto
-iobuf YES
-max_fanout 500
-bufg 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Yes
-use_sync_set Yes
-use_sync_reset Yes
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5

set -tmpdir "tmp"
set -xsthdpdir "xst"
-ifn <PROJECT>.prjise
-ifmt mixed
-ofn <PROJECT>
-ofmt NGC
-p xc3s500e-4-fg320 <- FPGA
-top <TOP_LEVEL>

Code:
$cat LED.prjise vhdl work "../src/frec_div.vhd" tariq786 ### tariq786 Points: 2 Helpful Answer Positive Rating #### srinpraveen ##### Member level 2 Thanks for those infos..Regarding icarus verilog, only ver 0.8 supports synthesis statements. In ver 0.9, support for synthesis has been removed. When I try to install icarus verilog through the ubuntu software center repositories, it installs only the latest version and there is no way wherein I can get the old version of icarus as far as what I can see. And I couldn't find any links for old version of icarus verilog package v0.8. #### srinpraveen ##### Member level 2 Thanks aarmalo..appears like there are lot of different variations of v0.8 like v0.8.4 , v0.8.6 etc.. which version do you recommend me to download? #### aarmalo ##### Junior Member level 1 srinpraveen ### srinpraveen Points: 2 Helpful Answer Positive Rating #### srinpraveen ##### Member level 2 Sure...Thanks a lot for your guidance aarmalo... #### aarmalo ##### Junior Member level 1 Download from Debian -- Details of package verilog in lenny (choose your architecture --end of page) Open a terminal if icarus verilog is installed then sudo apt-get remove verilog iverilog Now go to download dir and type sudo dpkg -i verilog_0.8.6-1_i386.deb <-- for x86 sudo dpkg -i verilog_0.8.6-1_amd64.deb <-- for x86_64 It work on Ubuntu 10.04 maybe work on 11.04 Code: $ iverilog -v
Icarus Verilog version 0.8.6 ($Name:$)
This program is free software; you can redistribute it and/or modify
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA

iverilog: No input files.
Usage: iverilog [-ESvV] [-B base] [-c cmdfile] [-g1|-g2|-g3.0]
[-D macro[=defn]] [-I includedir] [-M depfile] [-m module]
[-N file] [-o filename] [-p flag=value]
[-s topmodule] [-t target] [-T min|typ|max]
[-W class] [-y dir] [-Y suf] source_file(s)
See man page for details.

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#### srinpraveen

##### Member level 2
Okay..I will try it out...Thanks..

#### enchanter

##### Member level 2
I tried 13.2 on Ubuntu 11.04. Installation is fine. But when I run the license check or xinfo, I got "segfault error". During the implementation. I got failed on timing report generation.

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