Any suggestions on how to fine-tune the FPGA implementation

[jasonxie]

After the function simulation of the logic design is finished, I usually use FPGA synthesys tools like S*YNPLIFY to compile it into EDF file , then use FPGA Place&Route tools like X*ilinx ISE to generate PROM file and burn.

It looks like once the logic design is put into implementation procedure, there is limited way to fine tune the design itself -- mostly I can only carefully set constrains and options of these tools, just a rough control.

I can only improve design depend on the output report of S*YNPLIFY. But sometime there is always a conflict between the timing analysys from S*YNPLIFY and actual timing result after Place & Route. (S*YNPLIFY says OK, but X*ILINX run out a Fail timing).This suffers me a lot.

Any good idea to handle this? Thank a lot.

 

[snake]

hi,
when you compile the desining and verify that you are not view the real timing on gates that are just simulated after place and route
verify how many stages you have in your logic.
sorry about my poor english

 

[mart242]

Use the XIlinx constraint editor to specify the timing constraints of your design. You could also do some floorplanning, but it usually ends up making the problem worse.

If you still don't meed the timing, use the timing analyser to figure out what's wrong: improper placement, improper pipelining of the design, ...

 

[RTL2GDSII]

@ltera web site has an application note about timing closure !

 

[CatKing]

use the physical synth tools such as amplify(synplicity) and precision synthsis(mentor)

 

[Phytex]

Altera LogicLock

Hi,

with Altera you can tune your design with LogicLock at Quartus! I get sometimes a 5-12 % faster design with LogicLock from Altera. But I don't know if Xilinx also have tools like LogicLock!
But it is always the right way to make first an synthesys with Synplify Pro!

Phytex