i want to simulate PLL in abstract level. also, i want to get the simulation result similar to that of circuit level simulation. that is to say, i want to save the time and space of the simulation, while preserving the precision.
any suggestion on that?
at least, i want to simulate the phase noise/jitter of the output clock and the ripple of control voltage.
U may use matlab to simulate the phase noise, just write the correct equations of each block, which will depend on the PLL parameters, and it will draw the total phase noise for u.
i think verilog-a is very good you could write a code for both time and frequency domain .
and try this link i think it is valuable. https://www.designers-guide.org/VerilogAMS/