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Any experience in design small loop filter in PLL?

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hung_wai_ming(at) said:
As in the topic

simplest is the passive filter with caps and resister

forgive me that i always find someone answering not to the point.
Please see my topic. I ask "how to design a SMALL loop filter". I know the basics, OK?

what do u mean by small loop filter ? , is it integrated

or what do u mean ?


Charge pump current source is better.
You can decrease value of current and so to decrease value of filter capacitor and chip area.

I mean on-chip loop filter and basically, we need a large capacitor on -chip. So, my question is there any good way to reduce on-chip cap?

From eqn, reducing charge pump current will reduce damping factor as well, and if you further reduce cap value, how can your PLL be stable easily?

Hi ...i an currently deisgining a loop filter(passive for a pll.

The problem is the I need a loop bandwidth of 100k to 10M.
and also my charge pump current is variable and can be varied form 1uA to 64uA
and also the n divider has 256 stages.

can some one help me out on the following ....

I would like to know how the CP and N values would affect the loop bandwidth..
how would a variable R in the Loop filter help.


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