Another Challenging Problem in VHDL Design

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govandi999

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challenging vhdl designs

Design a Password feeder using behavioral VHDL. In this we have an 8-bit input DATA for the password. We have a signal called ENABLE. If ENABLE ='1' then the input data ie the password is read and loaded in a register. The input DATA is then compared to the data stored in a variable somewhere inside the code. 3 chances are given. if it fails three times then the output should display 'E' (Fail) on the seven segment decoder and if the password is correct, it should display 'S' (Pass)
 

Dude, if this is your homework, it's better you take from your friend. If it is work, this is your business. But if you really need help, try post some code, even if wrong, to we correct you. But, you are asking the code already implemented, without a little effort of you. Please, this is a forum to discuss, to learn, not to give code. Please, my friend, try different. I know you have goo intentions and don't take this to personal side.

Best Regards

Breno

P.S - you can look in shift register theory. Also, you probably will need a clock, to sync thing. Good vhdl practices programming uses a clock to work as sync mode.
 

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