Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

And Gate in Gated Clocks

Status
Not open for further replies.

spartanthewarrior

Full Member level 2
Joined
Jun 13, 2007
Messages
122
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Activity points
2,142
Hi All,

Why we use "AND" gate in gated clocks instead of "OR" gate.

Regards
 

how can you gate a clock using or gate because the clock is gonna propagate whether the other input is 1 or 0....
 

Because Gated Clock is used to stop the system clock to go through the logic block. If you use OR gate then it will always run through the block in any case. Therefore, it is wrong idea to use OR gate.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top