[SOLVED] Analog IC layout problem in UMC_18_CMOS techfile

[Deepon]

jm3395,

Thanks for the help, but it is a 3 terminal device...

dgnani -

I would agree that the psymbol layer is probably a recognition layer but it is part of the layer construction of the resistor whether it is a real physical layer or not. It was not clear to me whether the "Symbol" layer was indeed the red/orange layer (the label could have been moved to the wrong layer) and if it is just a marking layer, why draw it as big as it is ? Why not draw it as big as the physical resistor ? If the Symbol layer is the red/orange layer and it is a marking layer, why do you need the poly and metal ? The problem is that without the actual data in front of you, you can assume something incorrectly.

In any case, my assumption was that the red/orange layer is a real physical layer that needs poly/metal contacts and not part of the substrate. If I am incorrect, Deepon's answers will tell me that. I am well aware that you do not connect to a substrate with poly. I did mention in my earlier post that you need pdiff to connect to a p-substrate.

It would be helpful to have Deepon respond and clarify things so we can offer helpful advice.

---------- Post added at 15:14 ---------- Previous post was at 14:58 ----------

dgnani,

I had tried using the M1_PDiff but it is not completing the net connection..
I wonder if PDiffusion layer will be able to connect with the substrate..

There is something that is bothering me:

1. In the device level, the 'PLUS' & 'MINUS' terminal contains all the M1 to M5 & there corresponding via contacts placed upon each other.





Then why do I have to again add all the contacts of M1 to M5 on thos terminals in my circuit in order to complete the net connection.





If this can be solved, then perhaps we can decide that why M1_Pdiff is not completing the net.

I am looking at UMC_18 layers and I can tell you that all ?SYMBOL layers are device recognition layers.

You need the poly and metal (and SAB and NPLUS) because those are tapeout layers, necessary for mask preparation.

If you can find an example of physical layers that is not a metal and poly can connect to...

In any case you make a good observation, I had not noticed that there was poly under the B terminals' metal1

This means that those two are dummies (remember this is an RF device) so we still need to connect a p-contact to substrate (should be called something like M1_PDIF).

In summary forget about the previous suggestion of placing p implant rectangles around the B terminal and instead place an M1_PDIF contact (in real RF life you would probably use a guard ring but for now we just want a clean LVS) outside the device perimeter and connect it to gnd! with metal1

This should do the trick

 

[dgnani]

Hi Deepon,
you have not really shown us how you are performing the contact to substrate, M1_PDIF will contact the substrate and you should be able to probe it with Assura.

Having M1-5 in the terminal does not really make a lot of sense to me, but you can just contact any of those metal to secure a connection.

As of the multiple Mx_CAD rectangles are you sure those are on a pin layer? did you check the full layer purpose on the LSW (use LSW Options menu item to visualize the full layer name when hovering the mouse over the layer name)?

By the way I see in your list of devices you also have a non-RF flavor of this resistor, does that work normally? do actually need the RF version ?

 

[Deepon]

dgnani,

I am adding a M1_Pdiff Contact to the 'Body' to connect with the substrate.



Having M1-5 terminals makes sense when you are routing with M3,M4 or other higher metals. Having M1-5 in the device level helps a lot as we don't have to insert M1-M5 contacts on the upper level.

The MX_CAD layers are on the device level, I can confirm that.
And yes, I need the RF model of the resistor as I am going to design RF circuits in CMOS logic.

Hi Deepon,
you have not really shown us how you are performing the contact to substrate, M1_PDIF will contact the substrate and you should be able to probe it with Assura.

Having M1-5 in the terminal does not really make a lot of sense to me, but you can just contact any of those metal to secure a connection.

As of the multiple Mx_CAD rectangles are you sure those are on a pin layer? did you check the full layer purpose on the LSW (use LSW Options menu item to visualize the full layer name when hovering the mouse over the layer name)?

By the way I see in your list of devices you also have a non-RF flavor of this resistor, does that work normally? do actually need the RF version ?

 

[dgnani]

The M1_PDIFF contact is the right one but you cannot place it on top of the B terminal because there is poly under the metal, which will stop the contact from getting to substrate.
You have to put the contact besides the device and connect both B terminals to it with metal. M1_PDIFF cannot touch nor overlap poly.
If this an RF design, once you have confirmed that you get a clean LVS with a single contact, use a guard ring of M1_PDIFF around the device instead of a simple contact

 

[Deepon]

dgnani,

I don't know why poly would block the connection with the diff substrate as I can see several poly to metal contacts placed on both sides of 'B'. However, I did like you told. I have attached a screenshot for your better understanding. But still, the incomplete net remains..:???:

The M1_PDIFF contact is the right one but you cannot place it on top of the B terminal because there is poly under the metal, which will stop the contact from getting to substrate.
You have to put the contact besides the device and connect both B terminals to it with metal. M1_PDIFF cannot touch nor overlap poly.
If this an RF design, once you have confirmed that you get a clean LVS with a single contact, use a guard ring of M1_PDIFF around the device instead of a simple contact

 

[dgnani]

poly in is not in contact with the substrate it is isolated from it from so-called field oxide, which is everywhere you have no active layer (DIFF). To contact the substrate you need CONT (the same via used for poly), DIFF (an area w/o field oxide) and PPLUS (implant to make the metal to semiconductor contact ohmic otherwise you'd get a Schottky junction). If you put this on top of poly you create two problems: CONT stops at poly and never gets to DIFF, POLY now being on top of DIFF is recognized as an active device (DIFF on poly is a FET gate).

I still do not see where you placed your M1_PDIFF contact

 

[Deepon]

dgnani,

I have now labeled the picture so that you can find out the contact..

poly in is not in contact with the substrate it is isolated from it from so-called field oxide, which is everywhere you have no active layer (DIFF). To contact the substrate you need CONT (the same via used for poly), DIFF (an area w/o field oxide) and PPLUS (implant to make the metal to semiconductor contact ohmic otherwise you'd get a Schottky junction). If you put this on top of poly you create two problems: CONT stops at poly and never gets to DIFF, POLY now being on top of DIFF is recognized as an active device (DIFF on poly is a FET gate).

I still do not see where you placed your M1_PDIFF contact

 

[dgnani]

Hi Deepon,

I eventually decided to try it myself, added the UMC18 RF tech library and made a test layout for the RNNPO_RF device.
I used Calibre LVS because I do not have Assura. It worked immediately.

Best guess is that Assura rules are incorrectly written, it is not unheard of but somewhat rare. Do you have the latest version of those rules?
If you have access to Calibre I encourage you to try.

 

[Deepon]

I don't have access to calibre. I will try to contact Cadence help desk regarding this issue.. Lets c... Thanx dgnani for all the helps.,

Hi Deepon,

I eventually decided to try it myself, added the UMC18 RF tech library and made a test layout for the RNNPO_RF device.
I used Calibre LVS because I do not have Assura. It worked immediately.

Best guess is that Assura rules are incorrectly written, it is not unheard of but somewhat rare. Do you have the latest version of those rules?
If you have access to Calibre I encourage you to try.

---------- Post added at 12:41 ---------- Previous post was at 12:25 ----------

dgnani,

One thing I wanted to ask you. Can I create a particular resistance just from scratch in layout? Can't I just use poly with SAB layer and add contacts on both sides to connect with metal. Then I can extract the layout & calculate the resistance.. What are the components that I will need..

 

[dgnani]

sorry Deepon,

you might want to try with UMC too, foundry is usually responsible for broken rulefiles