At first the middle node of the resistors should be connected to the substrate line (usually sub! or whatever name you want if in your case you want to avoid global names) and NOT directly to VSS (yours gnd).
Check your tech manual for more details for how to implement the connection between sub! and VSS.In most cases (maybe all) we place a subc in schematic that models this connection and this also comes in layout after the respective update from assura.Do it and if the problem persists i will assist you further.
Hi jimito13
there is no subc device in UMC18, subc is common in IBM RF processes but I have not seen it elsewhere. In this (UMC) case connecting VSS to substrate is perfectly ok, unless special noise isolation is required.
Hi Deepon,
RNNPO is a n-implanted poly res on p-substrate so you need contacts implanted with p to contact substrate
RNPPO is a p-implanted poly res on nwell so you need a n-implanted contact to connect the third terminal of this device
I think you should simply connect ntap on nwell (if resistors lies on nwell) / ptap of psub (if resistors doesn't lies on nwell) to gnd. In each technology I worked with it was a scheme of substrate connection in layout for resistors.
there is no subc device in UMC18, subc is common in IBM RF processes but I have not seen it elsewhere. In this (UMC) case connecting VSS to substrate is perfectly ok, unless special noise isolation is required.
Hi Deepon
it looks like your pcell already has B terminals on M1 so it should be sufficient to use metal and no special contacts: how are you checking LVS?
hi Deepon
I don't use Assura so I cannot verify it is setup correctly.
If RNNPO is anything like the version available in my PDK it is on psub (just hide everythign but NWELL to verify)
Still it looks like your pcell already provides terminals for B on metal1 so the p contact is already in place.
I would simplifiy your test cell and try to instantiate a single resistor with three terminals, your problem could be
- how you are stamping your pins
- missing vias
Hi Deepon and jm
the pcell already has terminals contacting the pwell so there is no other p-diff contact to add.
One gotcha here (I just noticed) is that the two B terminal have to connected together otherwise you get a so-called soft-connect violation (in Calibre jargon): basically you have a stamped piece of metal that connects to substrate then an unstamped piece of metal that connects to the same substrate, this is in most rule files an LVS error
Please try that, re-run Assura and let us know
Deepon,
I use Assura all the time. From looking at your simplified test case, it may be that the substrate is not defined and labeled properly. The question is how does the LVS file (not the techfile) define the substrate ? If it just needs a pdiff area with contacts, then you need to have that with whatever label is associated with it. If this is your gnd, then the gnd label needs to be on the pdiff/cont. If you have the body also tied to gnd, then you should only need a metal connection to the pdiff contacts. It is hard to tell not knowing all your layers but does your first circuit have the pdiff and contacts ? Your simplified test case has a gnd connection coming out but where does it connect to the substrate ?
Many LVS files define the substrate to be everywhere where there isn't any well and you generally connect to it using some type of p-diffusion (assuming a p-substrate) by using contacts. The substrate does not have to be connected to anything else physically in your circuit.
If you can clarify what some of the layers are, I may be able to help further.
... Then there is a red/orange layer I am going to call the bulk (B) which is connected to by poly and metal (and I presume contacts also). The first question I have is - is the red/orange layer part of the substrate layer (light outline) ? If not, then you have two connections you need to make - one is to the bulk (B) node, which you do by the metal/poly contact areas but then you also need to connect to the substrate itself....
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