Do u have any experiences at analog design in 90nm such as opamp, bandgap, comparator?
In my hspice simulation results, the gate of MOS has current. Is it right, or the spice model is wrong?
It is difficult to consider this leakage current. Such as in bandgap, i designed a NMOS to work as cap, but the gate current would damage the performance of bandgap.
Could we simulate this leakage current exactly?
It is difficult to consider this leakage current. Such as in bandgap, i designed a NMOS to work as cap, but the gate current would damage the performance of bandgap.
Could we simulate this leakage current exactly?