Anything op-amp has been designed and tested to death i think! I'll do a short test list for the LM148, National's version of the 741.
Datasheet is here:
**broken link removed**
A quick look thru the EC table will tell you the test list - TYP is most likely not tested, or just a quick functional test. MIN/MAX are always tested. Any other parameters are guaranteed by the EC table.
1) Input offset voltage - max 5 mV.
-Put 1v on (+) terminal and loop output back to (-). Read ouptut voltage. should be .995 to 1.005v
2) Input offset current - max 25nA. Usually similar to #1, except now you put 10k or 100k in series with each input. If offset voltage is already known, measuring voltage drop across each resistor will give you Ios. (Difference between drop/R)
3) Input bias current - max 100nA. Average of the two currents measured in #2. Reuse measurements for both of these tests saves test time.
4) Input Resistance - min 0.8 MEG. Check Input bias current at 1V and 5V, Difference is bias currents gives Rin
5) Supply current. Set (+) to midrange (0v), loop Vout to (-) again. Measure Icc..
6) Large signal voltage gain. min 25V/mV. Says VOUT=+/-10v, so probably 10k/1k resistor divider in standard inverting configuration. Set Vin=1v, 0.995, and 1.005, and check for 10, 9.95 and 10.05, etc.
7) Amp-to-amp coupling. - TYP only, user gets no guarantee! A good test engineer will have swept the parts with AC 1kHz to 20kHz, found the worst point, and put a quick sanity check in their test to screen out gross defects. (But designers HATE yield loss due to typ, so they may make you take it out if it's a problem)
A bunch more TYP's, then a few more easy tests and you're done! I would estimate 300-500mS test time for each channel, so maybe 1-2seconds overall.. Hmm that seems too long for a 741 maybe.. I was testing dual DC-DC in 1 second at my old job - they contain about 10 amps, oscillator, logic, current limit, etc..
As an example of some source code for the test program, let's assume I have a set of relays that either loops back input-output clean, or with 100k on each input.
//--------------------------------------------------------
//Vos test
//--------------------------------------------------------
myrelay->open_relay(); // loop back clean signal
delay(3);// 3ms relay settle time
Vneg->set_voltage(1.0, RANGE_2_VOLTS);
delay(1); // 1ms voltage settle time
mynegative=measure_voltage(Vneg);//Get V(-)
mypositive=measure_voltage(Vpos);//Get V(+)
myoffset=mynegative-mypositive;
datalog(myoffset);
And so on...