An VHDL interview question

[AhmedIbrahim]

Dear All,

I was asked today in an interview this question, Why do we need to have the same operand sizes for addition in VHDL, while in multiplication we don't? however we expect that both the result of addition and multiplication be of a bigger size than the operands!

Meaning that if a is std_logic_vector(3 downto 0) and b is std_logic_vector(3 downto 0) and c is std_logic_vector(4 downto 0) and d is std_logic_vector(7 downto 0)

so c <= a+ b; -- This gives an error for size mismatch
while d <= a*b; -- This goes OK with the VHDL compiler.

Regards

 

[bhav]

Carry of the addition will set/reset the CarrY flag, so no need for extra bit in "c".

 

[AhmedIbrahim]

Could you explain what you mean by the Carry flag? What I understand you're saying that the addition will be synthesized into a full adder, and the full adder output will be 4 bits + one carry bit, correct? if so then how can I read this carry bit in VHDL?

 

[FvM]

Why do we need to have the same operand sizes for addition in VHDL, while in multiplication we don't?

The summands don't need to have the same length, but the sum must have the length of the larger summand.

The product length is sum of both factor's length.

 

[AhmedIbrahim]

The summands don't need to have the same length, but the sum must have the length of the larger summand.

The product length is sum of both factor's length.

Yes I do understand the constraints on the addition operands in VHDL, I'm just asking why it should be equal to the larger operand and not "Larger + 1"?, which means that It doesn't consider the carry out. We normally in our arithmetic calculations do consider that the size of the output from the addition of two bit vectors should be equals to the larger operand size +1. so Why doesn't VHDL account for that?

 

[permute]

Ahmed, the reason is because that's what VHDL does.

I suspect even the writers of VHDL couldn't bring themselves to changing:
cnt := cnt + 1;
to
cnt_pre := cnt + 1;
cnt := cnt_pre(cnt'range);

But in the end, VHDL made a choice and that is the main reason.

 

[FvM]

There are many cases, where you want an adder just to wrap around, without extending the bit length.

To avoid possible addition overflow, you have to extend the larger of both summands to length+1.