an error when running ISE.

errorhysdesignrules:368

THE ERROR is

ERRORhysDesignRules:368 - The signal <CLKDLL/PSINCDEC> is incomplete. The signal is not driven by any source pin in the design.
ERRORhysDesignRules:368 - The signal <CLKDLL/PSEN> is incomplete. The signal is not driven by any source pin in the design.
ERRORhysDesignRules:368 - The signal <CLKDLL/PSCLK> is incomplete. The signal is not driven by any source pin in the design.

Actually, i open the file CLKDLL.v in ISE installation directory, and can't find the pin "PSINCDEC, PSEN OR PSCLK". Why the tools report this kind of error.


Thanks!

David

physdesignrules:368

The error messages seem to indicate that ISE is trying to use a DCM or Digital Clock Manager as a DLL, but all the various inputs to the DCM are not connected.

My guess is that you are using a coregen file from a different logic family. Some FPGAs only have DLL other newer parts have the DCM that is really a DLL with lots of other features. If the CLKDLL.v was generated from an older FPGA family, then COREGEN would not hookup these missing inputs as they did not exist.

Open up COREGEN and re-implement for the FPGA family you are using. My guess is that the errors will go away after that.

--- Steve

P.S. Please remove the old files from the design folder first and remember to do the file cleanup before re-implementing. This keeps ISE from using the old files.