AllenD
Member level 5

Hi guys
can I ask a question?
I am designing a most basic amplifier: nmos differential input, pmos current mirror loading. The output terminal is only planning to drive a cap.
My simulation output is in the picture attached. The red is the output without a cap and the green is with a cap. We can see the green curve is way less ideal compare to red. My analysis is as follow: I believe that the green are curves, instead of lines, suggests that it is not slew rate limited (also agree with my hand calculation). So I suspect that the reason of of the bad performance was due to the RC constant: huge output resistance make the RC constant really bad.
I have read that if your amplifier only need to drive a cap, no additional low-impedance output stage is needed. Is this statement contradict my simulation result?
Thanks
Allen

can I ask a question?
I am designing a most basic amplifier: nmos differential input, pmos current mirror loading. The output terminal is only planning to drive a cap.
My simulation output is in the picture attached. The red is the output without a cap and the green is with a cap. We can see the green curve is way less ideal compare to red. My analysis is as follow: I believe that the green are curves, instead of lines, suggests that it is not slew rate limited (also agree with my hand calculation). So I suspect that the reason of of the bad performance was due to the RC constant: huge output resistance make the RC constant really bad.
I have read that if your amplifier only need to drive a cap, no additional low-impedance output stage is needed. Is this statement contradict my simulation result?
Thanks
Allen
