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Thanks for the link, but the file seems to be unavailable now. I recall finding a Am2910 source in Verilog on a italian page, it may be the same, but I also recall that it was a gate-level Verilog, and I need RTL. That Synopsys example may be what I'm looking for. What about VHDL to Verilog translators? Is something like that available? And, more important, is there available one that actually works?
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