always blocks and synthesis of RTL

[sun_ray]

Will the three following always blocks be synthesizable? If not, please provide the reasons. These three always blocks are part of three different rtls. Ther ar not in the same rtl. In the first always block, the Enable is a enable signal for a counter.

always @( posedge clk or negedge reset or Enable)

always @ (posedge clkA or negedge clkA or reset)

always @ (posedge clkE or negedge clkE)

 

[FvM]

None of the three complies to the templates for synthesizable Verilog (e.g. IEEE Std 1364.1)
- the event list of an always block modelling edge sensitive logic must contain only posedge and negedge events
- an event can't act on both edges

 

[rajavel.rv]

Hi, why u mixed with combinational and sequential logic in sensitivity list,

always @( posedge clk or negedge reset or Enable)

always @ (posedge clkA or negedge clkA or reset)


if using this always block sensitivity list means what will happened,

1. That enable signal rising edge pulse came at inbetween edge of the clk means the next rise_edge of the clk result cannot appeared correctly.
2. Its having a blocking and non blocking issue also,

Regards,
Rajavel

 

[ads-ee]

1. That enable signal rising edge pulse came at inbetween edge of the clk means the next rise_edge of the clk result cannot appeared correctly.
2. Its having a blocking and non blocking issue also,

1. Depending on the contents of the always block...it implies this is a asynchronously active low reset register with some asynchronous enable, which would simulate but won't be synthesizable. The second always can't be synthesized as there aren't positive and negative edge triggered flip-flops in any library I've seen. (maybe someone should make such a FF and patent it ;-))
2. Without any code following the always you can't say there are any blocking and non-blocking issues.

 

[FvM]

Regarding dual edge triggered flip-flops, I mean to remember that it's available in some CPLDs. Interestingly the IEEE standard for synthesizable VHDL (IEEE 1076.6) provides a syntax describing dual edge triggered FFs. But of course it's meaningless for all regular FPGAs that don't support the feature. And as far as I understand, Verilog IEEE Std 1364.1 isn't prepared to describe similar hardware, the document assumes there's only a single posedge or negedge event representing the clock.

 

[sun_ray]

Regarding dual edge triggered flip-flops, I mean to remember that it's available in some CPLDs. Interestingly the IEEE standard for synthesizable VHDL (IEEE 1076.6) provides a syntax describing dual edge triggered FFs. But of course it's meaningless for all regular FPGAs that don't support the feature. And as far as I understand, Verilog IEEE Std 1364.1 isn't prepared to describe similar hardware, the document assumes there's only a single posedge or negedge event representing the clock.

How to write the rtl then for a DDR system taking care that the system works in bith the positive and negative edge? How to represent in the always block that the clock works in both posedge and negedge?

Regards

 

[FvM]

DDR signals are generated and received by dedicated DDR-IO blocks, comprised of multiple registers and a multiplexer. Review the hardware handbook for your logic family or ASIC macro library.

The DDR-IO blocks have regular FFs internally, in so far they could be modelled in HDL. But because they are usually instantiated as low-level primitives, you don't need to model their internal, neither for synthesis nor simulation.