ALU that multiplies using asterix-Verilog

[uniquadrion]

Due to my previous post got deleted somehow, this is my second post.

Hello,

First of all, I have a project that can do;





It accomplishes all of this perfectly. However, now I need to edit my program in a way that it multiplies 2 numbers instead of add them (I will take out add function and replace it with multiply instead). I need to do this with arithmetic operator which is * operator, as my instructor required and he claimed that verilog would accept it. However I got stuck on this because my ALU doesnt use + arithmetic operator so its not as easy as changing operator, which contrasted with what he said. Here are some screenshots from my ALU code.









So to make long story short, I need the adder to be a multipler of 2 numbers with the asterisk (*) operator. I was told that it would be very easy due to changing the operator however my ALU code is not written with operators. Otherwise it would have been easier as my instructor mentioned.

This the circuit of my project;



and for more detail, here I attached my project.

View attachment CPU.zip

Let me know if you have a question about it.
Thanks!

 

[ads-ee]

It's because you implemented your 4-bit adder as a structural implementation...why did you do that instead of using a behavior RTL description? i.e. sum <= a+b;
This is a good example of why you never ever ever use structural design implementations unless you like having to do a lot more work for a minor change like + -> * and sum[3:0] -> prod[7:0]. But hey there is one guy on this forum that thinks using structural gate level code is more "efficient", so you're not alone.

I'm not even sure how you would create a 1-bit multiplier that you can instantiate multiple times to build up a 4-bit multiplier. I would have to look at all the equations for each individual bit and derive a generic 1-bit implementation.

 

[uniquadrion]

It's because you implemented your 4-bit adder as a structural implementation...why did you do that instead of using a behavior RTL description? i.e. sum <= a+b;
This is a good example of why you never ever ever use structural design implementations unless you like having to do a lot more work for a minor change like + -> * and sum[3:0] -> prod[7:0]. But hey there is one guy on this forum that thinks using structural gate level code is more "efficient", so you're not alone.

I'm not even sure how you would create a 1-bit multiplier that you can instantiate multiple times to build up a 4-bit multiplier. I would have to look at all the equations for each individual bit and derive a generic 1-bit implementation.

I see.. So structural design makes everything a lot harder if you were to change something from your code. If I knew behavioral design before, I would of gone with it. However, we were taught the structural design first. Here is my project if you would like to take a loot at it. It requires xilinx (I run version 8.2) but it think it should run with all the versions. Here is my project if you would like to take a look at it, and maybe tell me how should I go about doing it. If doing it with asterisk (*) is harder, I can also go with the shift register method (if it is easier of course)

-Thanks

 

[ads-ee]

Really? You don't know how to translate your code to equivalent behavioral Verilog code? Do you understand how your structural code works or what it's structure represents?

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Code Verilog - [expand]
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always @*
  case (op_sel)
    2'b00 : mux = a + b;
    2'b01 : mux = a - b;
    2'b10 : mux = a * b;
    2'b11 : mux = a * a;
  endcase;

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That would give you a behavioral mux with each input selecting a different operation, of course this is only an example and it won't have very good timing (i.e. will be very slow as it's entirely combinational).