CPU-EO Project Status | |||
Project File: | CPU-eo.ise | Current State: | Programming File Generated |
Module Name: | cpu4_6_sample |
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No Errors |
Target Device: | xc3s100e-4cp132 |
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59 Warnings |
Product Version: | ISE 8.2i |
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Sat Nov 29 17:28:22 2014 |
CPU-EO Partition Summary | |||
No partition information was found. |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Total Number Slice Registers | 190 | 1,920 | 9% | |
Number used as Flip Flops | 171 | |||
Number used as Latches | 19 | |||
Number of 4 input LUTs | 615 | 1,920 | 32% | |
Logic Distribution | ||||
Number of occupied Slices | 416 | 960 | 43% | |
Number of Slices containing only related logic | 416 | 416 | 100% | |
Number of Slices containing unrelated logic | 0 | 416 | 0% | |
Total Number 4 input LUTs | 618 | 1,920 | 32% | |
Number used as logic | 615 | |||
Number used as a route-thru | 3 | |||
Number of bonded IOBs | 14 | 83 | 16% | |
IOB Flip Flops | 5 | |||
Number of Block RAMs | 1 | 4 | 25% | |
Number of GCLKs | 1 | 24 | 4% | |
Total equivalent gate count for design | 70,960 | |||
Additional JTAG gate count for IOBs | 672 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | Sat Nov 29 17:27:26 2014 | 0 | 26 Warnings | 19 Infos |
Translation Report | Current | Sat Nov 29 17:27:35 2014 | 0 | 0 | 0 |
Map Report | Current | Sat Nov 29 17:27:45 2014 | 0 | 15 Warnings | 3 Infos |
Place and Route Report | Current | Sat Nov 29 17:28:01 2014 | 0 | 4 Warnings | 2 Infos |
Static Timing Report | Current | Sat Nov 29 17:28:07 2014 | 0 | 0 | 2 Infos |
Bitgen Report | Current | Sat Nov 29 17:28:18 2014 | 0 | 14 Warnings | 0 |
Secondary Reports | ||
Report Name | Status | Generated |
Xplorer Report |