Xilinx Design Summary

CPU-EO Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Total Number Slice Registers	190	1,920	9%
Number used as Flip Flops	171
Number used as Latches	19
Number of 4 input LUTs	615	1,920	32%
Logic Distribution
Number of occupied Slices	416	960	43%
Number of Slices containing only related logic	416	416	100%
Number of Slices containing unrelated logic	0	416	0%
Total Number 4 input LUTs	618	1,920	32%
Number used as logic	615
Number used as a route-thru	3
Number of bonded IOBs	14	83	16%
IOB Flip Flops	5
Number of Block RAMs	1	4	25%
Number of GCLKs	1	24	4%
Total equivalent gate count for design	70,960
Additional JTAG gate count for IOBs	672

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met