You don't instantiate the modules in the case statement, can't be done the language doesn't allow this. So get that out of your head. You're obviously thinking like a software programmer, where you can call some function in a case statement.
Code Verilog - [expand]
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// instantiated add module
ADD ADD_inst (
.A (a_data),
.B (b_data),
.A_PLUS_B (output_bus_of_your_add_module));// case statement is wrapped in some always block, (not shown)case(alu_sel)
`ALU_ADD : alu_result <= output_bus_of_your_add_module;
`ALU_SUB : alu_result <= output_bus_of_your_sub_module;
`ALU_SHL : alu_result <= output_bus_of_your_shift_left_module;//etc....endcase
There are three types of modelling in verilog- gate level, dataflow and behavioral.
I think you should use dataflow modelling, if you want to use module instantiation and then connect all instance acc to ur diagram.