ALU design in VERILOG

[Salil Vaidya]

I am making a 8-bit ALU using verilog. I have made all the modules and they are working separately. like an adder,subtractor,left shift,etc. But, now i have to combine them in my ALU. How can I do this??? If I make a mux, then how to connect all these separate modules to the mux??? plz help....

 

[mrflibble]

"I have made all the modules and they are working separartely."

How do you know they are working correctly?

 

[Salil Vaidya]

Because I tested all the individual modules by writing testbench.They are working fine.The problem i have is that how do i connect these modules to mu ALU???Baecause,my ALU should select the functionality of any 1 of these modules according to select line inputs...plz help

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I have made an adder,subtractor,increment,decrement,shift left,shift right.They are working fine.i checked the testbench.The trouble i m having is how do i connect these modules to my ALU.lyk if my select lines are 001,then my ALU should perform A+B,if select lines are 010,then it should do A-B.For this to happen,i need to connect my adder and subtractor to the alu.how do i do it???plz help

 

[ads-ee]

How about using google to look for verilog multiplexer?

 

[mrflibble]

Ah okay, I was just wondering if indeed you had run a testbench. Because I found it a bit odd if you were not able to connect modules together (a common problem these days it seems ), but were able to do a testbench.

Anyways, if your only problem is how to code a mux in verilog, take a look at this one: https://www.asic-world.com/examples/verilog/mux.html

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May I suggest you use the case statement method. That tends to be more readable after a while, as in when you add more stuff to the mux.

 

[Salil Vaidya]

yes...i used case statement.bt how do i instantiate the modules inside case statement???

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mrflibble ...i understand what you are saying...i also knw how to write case statement.bt my prob is inside case,i will hve to instantiate my individual modules ryt???how to do that???

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i m not getting how to instantiate the module inside case statement.plz help.

 

[mrflibble]

y
mrflibble ...i understand what you are saying...i also knw how to write case statement.bt my prob is inside case,i will hve to instantiate my individual modules ryt???how to do that???

You don't. You instantiate the modules OUTSIDE of the case statement. And before you ask, also outside of any always blocks.
Guess the question is about module instantiation after all...

Some examples:

https://www.asic-world.com/verilog/syntax2.html
https://www.asic-world.com/verilog/para_modules1.html

 

[Salil Vaidya]

ohk..so shld i declare it as wire before case statement...n use dat wire inside tha case?

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plz can u post the syntax???
basically,i will have to prepare a mux using case statement right???So,when i do it,for a particular combination of select lines, say for 000,my mux(ALU)should produce output of an adder.So, how do i write it???can i declare d output of the adder as awire and then use it???plz help mrfibble

 

[mrflibble]

I get the feeling we are discussing verilog 101 here. How can you not know this when you have already made a testbench for it, etc. Is this your homework, and the components and the testbench were already provided by someone else or something?

At any rate, post your adder code and the testbench you used for it. That maybe gives some idea what we are talking about here...

 

[Salil Vaidya]

this is code of my 8bit adder which i made instantiating 1 bit adder:

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module adder8bit(
    input [7:0] a,
    input [7:0] b,
    input cin,
    output [7:0] sum,
    output cout
    );
    wire w1,w2,w3,w4,w5,w6,w7;
    
    
    adder1bit fa1(a[0],b[0],cin,sum[0],w1);
    adder1bit fa2(a[1],b[1],w1,sum[1],w2);
        
   adder1bit fa3(a[2],b[2],w2,sum[2],w3);
    adder1bit fa4(a[3],b[3],w3,sum[3],w4);
    adder1bit fa5(a[4],b[4],w4,sum[4],w5);
    adder1bit fa6(a[5],b[5],w5,sum[5],w6);
    adder1bit fa7(a[6],b[6],w6,sum[6],w7);
    adder1bit fa8(a[7],b[7],w7,sum[7],cout);
    
 
 
endmodule

---

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this is the testbench code which i wrote for the adder and its working:

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module adder8bit_tb;
 
    // Inputs
    reg [7:0] a;
    reg [7:0] b;
    reg cin;
 
    // Outputs
    wire [7:0] sum;
    wire cout;
 
    // Instantiate the Unit Under Test (UUT)
    adder8bit uut (
        .a(a), 
        .b(b), 
        .cin(cin), 
        .sum(sum), 
        .cout(cout)
    );
 
    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;
        cin = 0;
 
        // Wait 100 ns for global reset to finish
        #100;
        a=8'b00110111;
        b=8'b10101100;
        cin=1'b1;
        
        
        // Add stimulus here
 
    end
      
endmodule

---

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My problem is dat in my ALU,my mux input should be all the outputs of my modules ryt???so dat it can select one of them as output of the ALU when i give a particular set of select lines.so my doubt is how will i instantiate these modules as inputs of my mux???i hve made this code on my own.i knw basic verilog.i just need help in dis.plz help....

 

[Rohitchampion]

You just have to call all those modules you have created in your main module(you have named it 'alu' i guess).
I hope you know calling one module in another module.

 

[Salil Vaidya]

can you please tell me syntax or post an example???

 

[Rohitchampion]

can you please tell me syntax or post an example???

I am posting one example here.
verilog code for 4-bit full adder.

module half_adder (output s,c, input x,y); //1-bit half adder
xor(s,x,y);
and(c,x,y);
endmodule

module full_adder (output s,c, input x,y,cin); //1-bit full adder
wire s1,c1,c2;
half_adder ha1(s1,c1,x,y);
half_adder ha2(s,c2,s1,cin);
or d1 (c,c2,c1);
endmodule

module adder(output [3:0]s,output cout,input [3:0]a,input [3:0]b,input cin); //4-bit full adder
wire w1,w2,w3;
full_adder f1(s[0],w1,a[0],b[0],cin);
full_adder f2(s[1],w2,a[1],b[1],w1);
full_adder f3(s[2],w3,a[2],b[2],w2);
full_adder f4(s[3],cout,a[3],b[3],w3);
endmodule

See, here I am calling half adder module in full adder module and then full adder in adder.
I hope this will help you.

All the best.

 

[Salil Vaidya]

rohit,dats what i have done in my adder code.i know how to call another module.bt if i hve to call smthng inside a case statement,how do i do it???

 

[Rohitchampion]

Ah, Sorry, I didn't see that.
And I am not getting your exact question.
Can you please describe about your ALU and it's functioning(its operations) so that I can get your question?

 

[Salil Vaidya]

my ALU is has 3 select lines.it will take 2 inputs a and b.according to select line inputs,it has to do a=b,a-b,a and b,etc.
so,i have made separate modules for adder,subtractor,and gate,shift left,etc.
so, basically now i will have to build a mux which will select one of these operations.bt,i m nt able to write this code using case statement as i will have to take any of the individual module inside the case statement.plz help.plz post the example or syntax

 

[Rohitchampion]

okay. Then it's very easy. You need not create all those modules separately. just give cases as
3'b000: output = a+b;
3'b001: output = a>>1;
blah
blah
blah

 

[nature0303]

make a new project and add all these relative .v files into the project, when you are testing the top module,it will automatically call all the submodules

 

[Salil Vaidya]

thanks rohit.actually this was given to me as home assignment.bt in the instructions to solve the assignment,it was given that you should make all the individual modules first and then use them in your design.so,thats why i thot if it said so in the instructions,how can it be so simple???because if i use the code like you said,it is hardly 30 lines.so,i dont think my prof would assign 100 points for such a simple project.so plz help.i m attaching images of the question.
https://obrazki.elektroda.pl/9171936300_1393507095.jpg
https://obrazki.elektroda.pl/4621289900_1393507097.jpg

 

[Salil Vaidya]

Plz help.i need to get this done.