Altium Hierarchical design basics

[panfilero]

I'm making a schematic, and I'm doing it vertical style with sheet symbols, from what I understand, ports are used to go into sheets, pass connectivity vertically, and net names are used within a sheet... but when I get within a sheet with a port and I tie that port to a net name, when I compile I get a warning... do I just ignore these warnings? What's wrong with tying a port to a net name? or similarly if I go into a sheet with a port, and I use multiple ports throughout the sheet to avoid wires all over the place I get errors for using multiple ports

 

[PCBcomponentlibraries]

Can you post a screen shot of what you are tying to do. I'm having trouble visualing it. And details of the error might help.

 

[backdrill]

If you can post an image of relevant to you question, we would be able to understand you better then give you a sound advice.
Can you do that for us?

For the mean time, you can read about the basics of Hierarchical designs in Altium using this link:
**broken link removed**

Have fun!

Never stop exploring. - The North Face

 

[anilrock87]

Go to Project/Project options in that go to options and set the net identifier scope

You can ignore warnings if u feel net to net connectivity is correct.