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Altium Designer - net segment length control

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Advanced Member level 3
Oct 24, 2005
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how do you guys control net segment lengths for compley net topologies in altium designer?
What i found is that it supports only total etch length control, and that is it.

The cadence allegro supports segment length nicely. the most advanced way in allegro is to select a net, export it to the signal explorer topology viewer, set up what topology we want, and whats are the segment lengths (min/max, or relative to each other in signal groups) in that.
i have not seen anything like that in altium.

for simple microcontroller boards it is not a problem, but for example if you want to design a jedec Jesd21C based DDR3 memory-down layout, i have a feeling that it is not possible with altium at all.

how would you implement these in altium?
1.) DDR3 memory-down, based on SODIMM standard: > (log in) > free standards > DDR1/2/3 > jesd21C files > JESD21-C > all of document > MODULE4_20_18
2.) Compact PCI host card: lengths between: cPCI connector to series resistor, series resistor to pullup, pullup stub, cpci connector to interface chip. On a host board, the clocking nets also have a complicated topology. if you have picmg2.0 spec, you can check the details.
3.) Intel chipset FSB: matched groups, where each signal has a package length which will be an offset in length matching. check this: page 43.

we use Allegro, but it would be nice to use Altium, since its easier to create designs with that, and more enjoyable. without these features i could not use Altium in my work, unfortunatelly. There are hundreds of segmenth-length-controlled signals on evey board we design...

i just found this in altium: "FROM TO EDITOR"
Probably this is what i was looking for.

can we use this in interactive routing as well?

is there a pdf which describes this feature in a more detailed way?

Entering "length matching" in the Altium Wiki gives you various related results.

In altium you have to get use to DRC settings there you can use different permutation to define rules (though I have not used the rules to define such matching but the little that I have used was very good). As FvM said you can login to Altium wiki , there you might get answers to your query.

but I think better use of DRC and Design Class settings will help you out.

Best of Luck!


hi i need to route and measure on the fly . the drc method is not too useful to match net segments.
especially when there are lots of them.

i had some progress, but its still not working. the altium wiki has very short descriptions about this.
1. created fromtos on the nets interesting.
2. created fromto classes: T-shaped net, the 2 upper branch lengths have to be equal on: same net and between different nets. one fromto class is one upper branch of the T.
3. design rule > matched net lengths: matching rule on one fromto class.
4. route them
5. interactive length tuning, tab to select "from rules > matching". it says no rules found.

i stuck here. why did it not find them?
the other thing is the fromtos/connections are still visible after routing them manually.

Added after 15 minutes:

this is a test pcb, for testing this feature in altium.

the net is:

                Mem1  Mem2
                  I        I

the goal is to match the net lengths on each fpga-mem-x connecton, and equalize the FPGA-mem1 and fpga-mem2 segmenth lengths.[/code]

i did some more research, and it appears to me that these things are not fully supported by altium.

current altium high speed design support:

What is supported:
-set from-tos (like allegro pin pairs)
-measure pin-to-pin trace lengths on nets, almost real time: PCB-panel from-to editor: after length tuning press escape from mode, then it shows the actual segmenth lenghts.

what is there but not seem to work very well:
-applying trace length or matching rules on from-tos or from-to classes. Which means rules on net SEGMENTHs. sometimes the rule ediror display a syntax error on from-tos, or ignores rules based on from-to classes.
-on screen bar only displays full-trace (allegro total etch length) length rules and measurements.
- the same problem as above with: heads-up display, DRC report, DRC panel, netlist_status report, PCB list.

What would be really needed for very high speed designs:
- these to support from-to rules : onscreen lenght bar, DRC report, DRC browser, netlist status report, PCB list
- import lenght and segmenth rules from excel spreadsheets, like intel and AMD trace length calculators
- export lenghts and segmenth lwngths to excel spreadsheets, like intel and AMD trace length calculators

-graphical net topology rule editor.

Altium doesnt seem to be interested in the high technology level electronics design industry, only in the lo-tech and mid-tech. its very sad. :-(

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