spit
Member level 2
via sizes
Hi,
Quick question:
1. On my PCB, in the region where a Altera Cyclone 2 fpga 672 FBGA and all that is directly connected to it, I require traces of 5mil (0.127mm), vias of 16mil (0.4mm) with holes of 8mil (0.2mm), place 5mil spacing.
All other regions of tbe board the trace varies from 0.2m to 1.5mm, with via changing from 0.2mm to 1.5mm. Setting trace width rules for distinct net such as power eg gnd, vcc, agnd .. is no problem.
How do you handle all the other signals, which say have a trace width of 0.2mm?
if the intention is after manual routing of few critical nets it to autoroute the rest.
Does anybody have a design rule example to do this type of thing?
2. Does anyone have an example of a custom fpga bga fanout rule, which fansout
pairs of rows on successive signal layers? top to bottom say.
With the possibility of having non-sequential signal layer fanout, eg top layer first, bottom layer next, first inner next and so forth.
Thanks in advance.
Spit
Hi,
Quick question:
1. On my PCB, in the region where a Altera Cyclone 2 fpga 672 FBGA and all that is directly connected to it, I require traces of 5mil (0.127mm), vias of 16mil (0.4mm) with holes of 8mil (0.2mm), place 5mil spacing.
All other regions of tbe board the trace varies from 0.2m to 1.5mm, with via changing from 0.2mm to 1.5mm. Setting trace width rules for distinct net such as power eg gnd, vcc, agnd .. is no problem.
How do you handle all the other signals, which say have a trace width of 0.2mm?
if the intention is after manual routing of few critical nets it to autoroute the rest.
Does anybody have a design rule example to do this type of thing?
2. Does anyone have an example of a custom fpga bga fanout rule, which fansout
pairs of rows on successive signal layers? top to bottom say.
With the possibility of having non-sequential signal layer fanout, eg top layer first, bottom layer next, first inner next and so forth.
Thanks in advance.
Spit