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Alternative to dynamic arrays in VHDL

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Mar 9, 2008
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I gather that it is not possible to specify the size of an array at 'runtime' (im guessing synthesis is probably VHDLs 'runtime' in reality) in VHDL.

I have designed a 'program' in which I want to pass two integers to a subprogram, it does processing and if necessary, it adds them to an array of other integers.

The thing is, I don't know how many of these pairs I am going to have, could be 10 could be 1000 (or more) depending on what input the FPGA gets (its not practical to try and predict this)

What is best practice in my situation, sure I could just make an array of 200,000 integers but id really rather not!


According to my experience, runtime change in the depth of array is not possible. The design will be synthesized with fixed depth and allocate only defined resources at once.

We have tried the same thing and also with flexible length of signal/variable. Although, what I can think in this case is that you can dump your array values into external memory (SDRAM) and loop it back into the design. There are many FPGAs with on-board RAM and Flash memory. Your SDRAM will run and be controlled by internal signals from VHDL.

I hope that may work. If so, let me know the result. I would also like to evaluate it.

Mukesh Patel (MS.-Digital Communication)
Enginner - FPGA & Systems Design
(R&D DSP & Communication Systems)

Hi mpatel,

Yes it definately looks like anything of variable size is a no-goer in VHDL.

Unfortunately external RAM isn't an option for me, that said, I am looking at MegaWizard built Ram blocks.

I'm thinking of compiling a few designs with the blocks of varying size included to see how much of the logic I would use with different word counts.

My problem with this though is, its no different to just setting the size of the array to 1000 or so is it? At the end of the day a similar amount of logic will be used, im not saving any processing power since I could just use a counter to determine how many of my elements I acctually want to access - its just exchanging the nasty looking "range 1 to 10000" for the overhead of having to manage memory elsewhere in the program.

At the moment im trying another solution to needing my few thousand ints stored (easier said than done!) though I will still need an array of instances of packages, but these will be of a low enough count that I can just create a fixed size array no matter how bad it looks.

I'll let you know what I think of the performance, or if I come up with anything else.

I'm glad you posted to tell me you've tried even if it does work as at least now I know to stop trying to figure out how to do it!

Hi pini_1,

That looks pretty useful; i'm not using memory for this project but I think it might come in handy with another one im doing.

An update as to where I am with the arrays:

I have built a small logic block in VHDL which uses a couple of arrays of integers to do some simple processing, and its not looking good!

The program takes about 10 minutes to synthesize and then its too big for the FPGA (Cyclone II - 8K+ gates so not small!).

My thoughts at this point are that I was very wrong when I stated above that declaring arrays/records in VHDL was equivalent to using memory function blocks.

I think that at this point the best plan is to try and remove the need for storage of any serious size from the design altogether.

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