sebmaster
Member level 1
Hello,
I gather that it is not possible to specify the size of an array at 'runtime' (im guessing synthesis is probably VHDLs 'runtime' in reality) in VHDL.
I have designed a 'program' in which I want to pass two integers to a subprogram, it does processing and if necessary, it adds them to an array of other integers.
The thing is, I don't know how many of these pairs I am going to have, could be 10 could be 1000 (or more) depending on what input the FPGA gets (its not practical to try and predict this)
What is best practice in my situation, sure I could just make an array of 200,000 integers but id really rather not!
I gather that it is not possible to specify the size of an array at 'runtime' (im guessing synthesis is probably VHDLs 'runtime' in reality) in VHDL.
I have designed a 'program' in which I want to pass two integers to a subprogram, it does processing and if necessary, it adds them to an array of other integers.
The thing is, I don't know how many of these pairs I am going to have, could be 10 could be 1000 (or more) depending on what input the FPGA gets (its not practical to try and predict this)
What is best practice in my situation, sure I could just make an array of 200,000 integers but id really rather not!