Altera PLL - modelsim waveform

[shaiko]

My design has a PLL embedded in it - this PLL works properly on a synthesized Cyclone IV FPGA.
However, when I try to simulate - it doesn't work.

Attached are 3 files:

1. altera_mf.txt - megafunction library.
2. new_pll.txt - instantiations of the PLL at question (as configured by Altera's Megawizard)
3. tb_new_pll.txt - test bench for the new_pll.txt file.
4. pll.png - modelsim waveform snapshot.

In pll.png you can see "c0" and "locked" as undifined.
The file extensions have been renamed to .txt to allow uploading - please change them to .vhd

 

[K-J]

You don't have the file that includes the entity/architecture for the component altpll. This can be located at <Install_Directory>\quartus\eda\sim_lib\altera_mf.vhd

Kevin Jennings

 

[shaiko]

Added "altera_mf.vhd" to my project and tried to compile. It fails with the following errors:

-- Compiling entity sld_signaltap
** Error: C:/Users/Shaik/Desktop/pll_simulation/altera_mf.vhd(52290): (vcom-1136) Unknown identifier "SLD_IR_BITS".

** Error: C:/Users/Shaik/Desktop/pll_simulation/altera_mf.vhd(52290): Bad expression in left bound of range expression.
** Error: C:/Users/Shaik/Desktop/pll_simulation/altera_mf.vhd(52290): Type error in range expression.
** Error: C:/Users/Shaik/Desktop/pll_simulation/altera_mf.vhd(52292): (vcom-1136) Unknown identifier "SLD_IR_BITS".

** Error: C:/Users/Shaik/Desktop/pll_simulation/altera_mf.vhd(52292): Bad expression in left bound of range expression.
** Error: C:/Users/Shaik/Desktop/pll_simulation/altera_mf.vhd(52292): Type error in range expression.
** Warning: C:/Users/Shaik/Desktop/pll_simulation/altera_mf.vhd(52292): (vcom-1346) Default expression of interface object is not globally static.

** Error: C:/Users/Shaik/Desktop/pll_simulation/altera_mf.vhd(52316): VHDL Compiler exiting

- - - Updated - - -

Ignore the last message - I fixed it

 

[ads-ee]

Added "altera_mf.vhd" to my project and tried to compile. It fails with the following errors:
- - - Updated - - -
Ignore the last message - I fixed it

You shouldn't have had to add "altera_mf.vhd" to the project, it should be part of the Altera compiled/pre-compiled libraries. You can call those out on the vsim command line or add them to the library call outs in the modelsim .prj or .ini file (depending on which you use).

 

[shaiko]

You shouldn't have had to add "altera_mf.vhd" to the project, it should be part of the Altera compiled/pre-compiled libraries.

Even if I don't use the Modelsim version supplied by Altera ?

 

[ads-ee]

Hence the compiled(you compile the libraries)/pre-compiled(Altera compiled them).

I suspect you didn't follow the simulation setup mentioned in the Altera documentation. That doc tells you what libraries to compile and what they should be named.

 

[shaiko]

Your suspicion is correct - can you please post a link to this document ?

 

[ads-ee]

https://www.altera.com/literature/hb/qts/qts_qii5v3.pdf
It's in here somewhere, but I haven't looked in this doc for some years now, so they could have removed it.

You might want to bookmark this location:
https://www.altera.com/literature/lit-qts.jsp

 

[FvM]

The most popular reason for PLL simulation failure is that you didn't set a sufficient small simulation timestep, e.g. 1 ps. This results in no PLL operation without obvious errors. All other problems, e.g. missing libraries etc. gives significant warning messages like "component not bound" or errors.

Regarding libraries, ads-ee has mentioned the relevant points, you need to compile the Altera simulation libraries, if not already installed initially as with the Modelsim Altera Edition.

 

[ads-ee]

The most popular reason for PLL simulation failure is that you didn't set a sufficient small simulation timestep, e.g. 1 ps. This results in no PLL operation without obvious errors.

Thanks for pointing that out, I thought of that, went and got some tea and promptly forgot to mention it. I've been there don't that, when I've forgotten to change the timescale.

 

[mrflibble]

Mmmh, any references to the PLL simulation + timescale thing? Looks like I haven't gotten bitten by that through sheer luck, because I sure didn't know that one. Is that for Altera in particular, or simulation of PLL fpga parts in general?

 

[ads-ee]

Both Altera and Xilinx PLL modeling requires timescales of 1ns/1ps (I normally use 1ps/1ps as I haven't seen any appreciable difference in simulation performance compared to 1ns/1ns) I've looked at them an it's because of the delays they use to "lock" to the input clock. I'm sure if they start supporting 1GHz PLLs we will have to start using 1fs/1fs timescales ;-)

 

[shaiko]

The most popular reason for PLL simulation failure is that you didn't set a sufficient small simulation timestep, e.g. 1 ps. This results in no PLL operation without obvious errors. All other problems, e.g. missing libraries etc. gives significant warning messages like "component not bound" or errors.

I actually did encounter an error because of that...it was pretty easy to fix as the message pointed to a line in Altera's library that used a delay of 0.1ns - as soon as I changed the resolution to 1ps it started to work.

- - - Updated - - -

One more question:

You can call those out on the vsim command line or add them to the library call outs in the modelsim .prj or .ini file (depending on which you use).

As I'm not very familiar with Modelsim's inner workings...what is the difference between both files?
You're saying I can use one instead of the other?

 

[ads-ee]

If you use project mode, adding all your files in the GUI, then Modelsim uses the .prj file for holding all the information about your design.

If you don't use a project, basically just use the command line or open Modelsim without a project and compile your design using a do file script then the default will be to use an .ini file in the current directory or create a project file from the .ini file in the Modelsim installation directory (if there wasn't an .ini file in the current directory).

Now most of what I've written is observations from using Modelsim over the years.