The behaviour is surely exactly specified in the datasheet. You didn't mention a specific Altera FPGA family, but all Altera FPGA have week pull-up for unconfigured I/O pins.
A pull-down resistor will always solve the problem, but it must be dimensioned appropriately. For example, in case of Cyclone III family, it must be as low as 1k or even 470 ohm to achieve LVTTL low level safely over the expectable type variations.
A straightforward solution is to use exclusively active low level for all critical signals.