I've not used Altera SERDES, but designed many SERDES in the 70's (DS1 BER Test sets etc)
1) Normally bit clock VCO runs at 2f with quadrature 1f outputs, quadrature (90deg) 1clocks should be available. Pre-Comp, may help improve SNR or jitter reduction, but watch out for ISI and group delay distortion. Plan on doing BER margin testing for ISI at bit sync, word sync and frame sync levels. I see this chip has programmable thresholds for frame sync lock/unlock counts.
2) 10 bit sync pattern circuits are included, but not sure how frame clocks are generated. There is a manual bit-slip cct. and a Enhanced deterministic latency feature in Arria V devices.
The chip spec generalizes how to do bit sync , buffered FIFO word sync and unbuffered Direct SYNC but not sure which is best for you.
It must be possible with this chip to do all you request, but it would take me more than 15 minutes or even a few days to comprehend all specs.
Altera Hotline or Forum is best bet.
Are you using the Interlaken Protocol?
I wouldn't want to cut my teeth on this chip as my 1st SERDES design without an appreciation for eye-pattern tests, frame false sync pattern testing and some experience in fault injection with injected jitter margin tests.