Altera FPGA PLL and Serdes

[shaiko]

Hello,

Clock A is an input to an Altera Aria V FPGA.
I want to use a PLL to generate 2 internal clocks out of clock A:

1. Clock B - which is clock A shifted by 90 degrees.
2. Clock C - which is X2 of clock A (without a phase shift).

Plot thickens...clock A is also the timing signal of a serial data stream.
10 serial bits for every clock A cycle.

I want it to be the synchronization signal of a SERDES and parallelize the incoming stream.

Is it possible to use clock A for the generation of clocks B & C while at the same time it will sync a SERDES ?

 

[FvM]

There are two ways to share a user defined PLL with a SERDES block (ALT_LVDS_xx):
- define the SERDES with external PLL usage and generate the respective clocks in your PLL.
- use SERDES with internal PLL and same input clock as the user PLL. Try if Quartus can merge both PLLs into one.

 

[shaiko]

Thanks.
Another question.

Suppose I have a TMDS (HDMI) serial bit stream.
The pixel clock is 144Mhz.
Between every pixel clock cycle - 10 serial bits are arriving.
I.E - the actual bit clock is 1440MHz.

I want to parallelize the incoming data with a SERDES (1:10 gear).
Can I use a PLL to multiply the pixel clock by 10 and than use the newly created 1440MHz clock as the reference clock for the SERDES ?

 

[FvM]

SERDES will use DDR registers and a 720 MHz clock in this case. Need to check if your FPGA family supports the speed.

 

[shaiko]

Need to check if your FPGA family supports the speed.

Suppose it does...
So I have to generate a 720MHz clock with the PLL and use it as a reference for the SERDES?

 

[FvM]

The SERDES PLL generates two clocks, slow frame clock (word rate) and fast bit clock (half bit rate)

 

[shaiko]

The SERDES PLL generates two clocks, slow frame clock (word rate) and fast bit clock (half bit rate)

What do you mean by: "The SERDES PLL generates two clocks" ?
Isn't it the designers job to generate the resentence clock (via PLL) for the SERDES ?

 

[FvM]

"the SERDES PLL generates" refers to an ALT_LVDS_xx setup with internal PLL. If you supply the clocks yourself in external PLL mode, they need to have the same characteristics.

 

[shaiko]

Attached is a snapshot of Quartus.
I've chosen the SERDES to have a 1:10 gear ratio and left the "use external pll" box unchecked.

In the next page, the wizard allows me to set the datarate. But Per given datarate, it allows me to select a wide range of input clock frequencies (see the dropdown menu) .

Question: Why?
Assuming a fixed gear ratio and a given datarate - it seems that Quartus should know the input clock.

 

[FvM]

If the input clock frequency is not equal to the SERDES slow clock (output word rate), or an integer part of it, the input clock can't be used for frame synchronization, you need a different synchronization means.

You didn't yet talk about your application, how the frame (and possibly bit) synchronization is achieved.

 

[shaiko]

I don't understand your answer.

1. Quartus knows that the gear ratio is 1:10 (I.E - 10 bits per frame)
2. It also knows that the data rate is 1440MHz.

Why does it give possible clock values other than 144MHz ?

 

[FvM]

Because you can use different input clocks and synchronize the frame clock by other means, e.g. by the bit slip feature. The question can't be actually answered without considering your application requirements (and in some regards the FPGA type).

As a simple example, if you'll use the ALT_LVDS_RX block to receive data from a LVDS ADC, the input clock will be usually the ADC FCO output, and it's frequency equal to the word rate.

 

[D.A.(Tony)Stewart]

I've not used Altera SERDES, but designed many SERDES in the 70's (DS1 BER Test sets etc)

1) Normally bit clock VCO runs at 2f with quadrature 1f outputs, quadrature (90deg) 1clocks should be available. Pre-Comp, may help improve SNR or jitter reduction, but watch out for ISI and group delay distortion. Plan on doing BER margin testing for ISI at bit sync, word sync and frame sync levels. I see this chip has programmable thresholds for frame sync lock/unlock counts.

2) 10 bit sync pattern circuits are included, but not sure how frame clocks are generated. There is a manual bit-slip cct. and a Enhanced deterministic latency feature in Arria V devices.

The chip spec generalizes how to do bit sync , buffered FIFO word sync and unbuffered Direct SYNC but not sure which is best for you.

It must be possible with this chip to do all you request, but it would take me more than 15 minutes or even a few days to comprehend all specs.

Altera Hotline or Forum is best bet.

Are you using the Interlaken Protocol?

I wouldn't want to cut my teeth on this chip as my 1st SERDES design without an appreciation for eye-pattern tests, frame false sync pattern testing and some experience in fault injection with injected jitter margin tests.

 

[shaiko]

Are you using the Interlaken Protocol?

No.
As I mentioned in #3.
My question is about HDMI...
The pixel clock is 144MHz and 10 bits arrive per cycle.

How would you configure the SERDES in that case ?

 

[FvM]

Obviously, you'll configure the SERDES PLL for 144 MHz input clock, 720 MHz "fast" and 144 MHz "slow" clock.

 

[shaiko]

Obviously, you'll configure the SERDES PLL for 144 MHz input clock, 720 MHz "fast" and 144 MHz "slow" clock.

But this 720 MHz clock is invisible to me, it's internal to the SERDES mechanism - correct ?
I only set the input clock (drop down menu) to 144MHz and the tool does the rest?