Altera CycloneII Bidirectional Pin Assignment

[nag123]

altera bidirectional

Hi all,

I am new to altera FPGA design. I have got a problem on bidirectional io pin assignment. I have interfaced Altera CyclonII FPGA with a processor. The processor is able to write the data to FPGA. It's not reading FPGA data. All control srtrobes rd_en, wr_en and cs are ok.
I have a doubt whether I assigned data bus correctly or not. Can anyone suggest me how to assign bidirectional pins? Do I need to set any constraint in assignment editor?

Thanks

 

[mmarco76]

@ltera CycloneII Bidirectional Pin Assignment

You don't need any FPGA constraint, but it's pure VHDL code.
In the FPGA you can always read the data so

DATA_IN <= CPU_DATA_BUS;

But you need to set the bus in treestate when you don't need to write (in this example CS is active high, so when it's active you can put your data out else you need to keep the bus in treestate).

CPU_DATA_BUS <= DATA_TO_OUT when (CS='1') else (others => 'Z');

Hope it helps

 

[karikalan_t79]

check the pin planner , does it correctly instatiate bidir pin for the particular pin, otherwise, just add it