Altera configuration Problem?? Help

[Bajaj]

Hello

I have board with Altera stratix FPGA. Because of board design mistake, MSEL[2:0] are always logic 1. I can not cut or modify because tarce are not visible (burried).

Can i use this board? if yes what configurtaion i should use. can i use JTAG configuration?

Thanks

 

[davorin]

Why are people always to lazy reading the datasheets??????

Page 1832 of the Stratix handbook says it clearly:

JTAG-based configuration takes precedence over other configuration schemes, which means the MSEL pins are ignored.

And also "111" doesn't belong to any configuration scheme...so JTAG is your last hope...


RTFM!