Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Also questions about bandgap:

Status
Not open for further replies.

jcpu

Full Member level 4
Joined
Dec 17, 2005
Messages
215
Helped
18
Reputation
36
Reaction score
6
Trophy points
1,298
Activity points
2,968
(1) quite some literature about BGR using MOSFET in weak inversion
instead of parasitic BJT. How do they behave in real product?

(2) we use LDO + BGR to avoid PSRR problem.
LDO output to BGR,
meanwhile input reference voltage of LDO
is taken from the output of BGR
We did check startup by transient.
But still wondering if this a good common practice?

Thanks in advance.
 

ambreesh

Full Member level 5
Joined
Feb 21, 2005
Messages
319
Helped
21
Reputation
42
Reaction score
4
Trophy points
1,298
Activity points
4,347
Correct me if I am wrong, this is what I understand from your 2nd question
I am not sure that bGR in LDO is used for PSRR improvement.
Are you suggesting that BGR is used for PSRR improvement in LDO.
 

jcpu

Full Member level 4
Joined
Dec 17, 2005
Messages
215
Helped
18
Reputation
36
Reaction score
6
Trophy points
1,298
Activity points
2,968
Dear Ambreesh:

LDO to prevent VDD noise or change from affecting BGR behavior
by more or less fixing supply voltage to BGR.
Basically that is the picture in original designer's mind.
But we wonder if this is a common practice
or there is better way to achieve same goal.

Thanks.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top