Allowing integer overflow in VHDL

[vvanders]

vhdl overflow

I'm in the process of converting a design from verilog to VHDL, one of the parts of my design contains a circular buffer that was just using a counter that would rollover back to 0 when it overflowed in verilog.

Is there any easy way to do this in VHDL? I'm using a integer type, "read_cnt : integer DEPTH-1 to 0" for my variable but the simulator throws a index out of bounds when I run it and the value goes path DEPTH-1.

 

[shanmugaveld]

vhdl integer

I dont knw abt integer...
Instead of integer use std_logic_vector. this mwy helpful for u..

 

[alexadmin]

vhdl integer overflow

Is there any easy way to do this in VHDL? I'm using a integer type, "read_cnt : integer DEPTH-1 to 0" for my variable but the simulator throws a index out of bounds when I run it and the value goes path DEPTH-1.

signal read_cnt : integer range 0 to DEPTH-1:=0;
...
if(read_cnt = DEPTH-1) then
   read_cnt <= 0;
else
   read_cnt <= read_cnt + 1;
end if;

 

[vvanders]

overflow in vhdl

I was hoping I wouldn't have to do that and VHDL would have a much more C like handling of integers, ah well.