vvanders
Newbie level 4
vhdl overflow
I'm in the process of converting a design from verilog to VHDL, one of the parts of my design contains a circular buffer that was just using a counter that would rollover back to 0 when it overflowed in verilog.
Is there any easy way to do this in VHDL? I'm using a integer type, "read_cnt : integer DEPTH-1 to 0" for my variable but the simulator throws a index out of bounds when I run it and the value goes path DEPTH-1.
I'm in the process of converting a design from verilog to VHDL, one of the parts of my design contains a circular buffer that was just using a counter that would rollover back to 0 when it overflowed in verilog.
Is there any easy way to do this in VHDL? I'm using a integer type, "read_cnt : integer DEPTH-1 to 0" for my variable but the simulator throws a index out of bounds when I run it and the value goes path DEPTH-1.