maverick1989
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Hello,
I'm going to be very descriptive because it is a strange error that I am getting.
I am using Allegro 16.3 to design a multi-layer board. I have four different blind vias defined. They go from the top layer to the two immediate inner layers and the bottom layer to the two immediate lower inner layers. So if layers are numbered 1-12, I have L1-L2, L1-L3, L11-L12, L10-L12 vias. All other layers are connected by through hole vias.
The problem is, the tool does not think that a trace on layer 2 passing over a L1-L3 via is a problem. Basically no buried via shows DRC unless there is a clearance violation between traces residing on the two layers the via is connecting. So for the above mentioned L1-L3 via, a trace on the top (L1) layer will show a DRC if it violates the constraints set in the CM. The same goes for L3. But a trace on Layer 2 will pass right over this via without any errors. This is a big trouble to fix unless the tool starts showing DRC because I have over 400 vias to look at to see if a layer 2 trace (or layer 11 trace) is passing over a L1-L3 (or L10-L12) via.
As a further note, all vias have been defined in the CM. B/B via to everything else constraints have been set according to the fabrication company's specifications. Similarly, traces to all via constraints have also been accordingly set. The B/B via is defined by adding circular pad to the two layers it connects and then setting the bottom layer pad to null.
Any help on this would be appreciated.
Thank you.
I'm going to be very descriptive because it is a strange error that I am getting.
I am using Allegro 16.3 to design a multi-layer board. I have four different blind vias defined. They go from the top layer to the two immediate inner layers and the bottom layer to the two immediate lower inner layers. So if layers are numbered 1-12, I have L1-L2, L1-L3, L11-L12, L10-L12 vias. All other layers are connected by through hole vias.
The problem is, the tool does not think that a trace on layer 2 passing over a L1-L3 via is a problem. Basically no buried via shows DRC unless there is a clearance violation between traces residing on the two layers the via is connecting. So for the above mentioned L1-L3 via, a trace on the top (L1) layer will show a DRC if it violates the constraints set in the CM. The same goes for L3. But a trace on Layer 2 will pass right over this via without any errors. This is a big trouble to fix unless the tool starts showing DRC because I have over 400 vias to look at to see if a layer 2 trace (or layer 11 trace) is passing over a L1-L3 (or L10-L12) via.
As a further note, all vias have been defined in the CM. B/B via to everything else constraints have been set according to the fabrication company's specifications. Similarly, traces to all via constraints have also been accordingly set. The B/B via is defined by adding circular pad to the two layers it connects and then setting the bottom layer pad to null.
Any help on this would be appreciated.
Thank you.
