Allegro PCB Editor not showing DRC for B/B vias

[maverick1989]

Hello,

I'm going to be very descriptive because it is a strange error that I am getting.

I am using Allegro 16.3 to design a multi-layer board. I have four different blind vias defined. They go from the top layer to the two immediate inner layers and the bottom layer to the two immediate lower inner layers. So if layers are numbered 1-12, I have L1-L2, L1-L3, L11-L12, L10-L12 vias. All other layers are connected by through hole vias.

The problem is, the tool does not think that a trace on layer 2 passing over a L1-L3 via is a problem. Basically no buried via shows DRC unless there is a clearance violation between traces residing on the two layers the via is connecting. So for the above mentioned L1-L3 via, a trace on the top (L1) layer will show a DRC if it violates the constraints set in the CM. The same goes for L3. But a trace on Layer 2 will pass right over this via without any errors. This is a big trouble to fix unless the tool starts showing DRC because I have over 400 vias to look at to see if a layer 2 trace (or layer 11 trace) is passing over a L1-L3 (or L10-L12) via.

As a further note, all vias have been defined in the CM. B/B via to everything else constraints have been set according to the fabrication company's specifications. Similarly, traces to all via constraints have also been accordingly set. The B/B via is defined by adding circular pad to the two layers it connects and then setting the bottom layer pad to null.

Any help on this would be appreciated.

Thank you.

 

[sivamani]

pls do the following:
1. Check whether auto update DRC option is enabled or not...
2.check the same net rule if you routing same net on the via...
3.do database check once
4.check the via definitions once gain..

 

[maverick1989]

Thank you very much for your response.

pls do the following:
1. Check whether auto update DRC option is enabled or not...

I have manually clicked "Update DRC" several times. Also, I had to change a particular clearance in the CM and when I changed it, several DRCs popped up so I'm assuming this one is taken care of. However, I will check once again.

2.check the same net rule if you routing same net on the via...

No none of these are issues with the same net. These are for different nets

3.do database check once

I will try this.

4.check the via definitions once gain..

I have rechecked these several times. I'll describe how I have defined them. Please let me know if this is not the convention. For B/B vias (I will take L1-L3 as an example), I have set "Regular pad" to "circle". In the radius, I have set it to the fab's recommendation. This regular pad is set to circle only on L1 and L3. On L2 as on all other layers except L1 and L3, the value is set to "Null". So effectively, what should happen is that a large pad should exist in the connection layers and only a drill on the layers in between. Is this correct? Or should I set the pad on the middle layer to circle but a radius of the same value as the drill value?

Again, thank you. I will try your suggestions.

 

[maverick1989]

So I did everything sivamani suggested. No luck. I can still route a trace on layer 2 right through a via between layer 1 and layer 3 and the tool doesn't think it is a problem. Does anyone else have any other suggestions? This is kind of a big overlook if it is a bug in the tool. I am going to go through it all but there is always a high probability to overlook one via and then the fab comes back to me annoyed. I would appreciate any help.

Thank you.

 

[sivamani]

check the via definition is constraint manager what it is showing..you can see the via structure while ur assigning via in constraints (cmgr).

I have enclosed the snap shot for defining BB via in allegro.Pls check whether have u defined in the same way or not...