All transistors in the cutoff region

[aishakhan]

Hi, I'm simulating my design for designing an Instrumentation amplifier, but for some reason at this first stage where I have a transconductance amplifier with current mirror load and current source biasing, I've simulated the design in Virtuoso, but for some reason, all my transistors appear to be in cutoff region. Could someone please tell me what is wrong with my circuit?
Also, this is a design chosen from this paper: https://ieeexplore.ieee.org/document/5635368 If anyone could help me with what is wrong with my design, I'd be grateful as I'm new to analog IC design. The circuit is shown below:

 

[FvM]

Apparently no useful current setting for bias source I0.

 

[aishakhan]

Yes, you were right, I didn't give any current setting for the current source I0. Thank you so much it worked.