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Transistors in power supplies.

joniengr

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Hi,

I am trying to understand this schematic which is from a FPGA development board. There is a connector J15 and a on/off switch SW1. The signal from the J15 connector is VCC12_P which is connected to the transistor Q1 and also to the switch SW1 at pin number 1. The pin number 2 of the switch SW1 is then connected to an other transistor Q4. I am not sure what are the functions of these two transistors.

The drain signal from the transistor Q1 is then connected to a EMI filter U16 and then a LED DS26 is connected at VCC12_SW with a resistor R460 to ground. This part is understandable but what are the role of transistors Q1 and Q4 in the schematic.

Untitled 100.png
 

betwixt

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The current flowing in to Q4 gate is negligible so there is no load on the switch or whatever else is connected to "MASTER SW 12V". Q4 is an enhancement mode device so a high level on its gate will cause conduction between drain and source causing the drain to drop to almost GND potential. R316 and R273 then cause the gate of Q1 to go more negative with respect to its source, turning it on.

So basically, it's a solid state on/off switch to the "VCC12 SW" line.

Brian.
 

joniengr

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The Q4 BSS138 is n-channel MOSFET that means when Vgs is more than 1.3 V (from datasheet) then the MOSFET conduct and act as a close switch, right ?

But how about Q1 FDS6681Z, any reason for more than one pin for drain and source ? is that because of current ?

The Q1 FDS6681Z is p-channel and this MOSFET will conduct and act as close switch when Vgs is negative, right ?

But what is the purpose of these introducing these MOSFET Q1 and Q4 in the power circuit. There is already a physical switch SW1 which is manual switch.
--- Updated ---

The current flowing in to Q4 gate is negligible so there is no load on the switch or whatever else is connected to "MASTER SW 12V". Q4 is an enhancement mode device so a high level on its gate will cause conduction between drain and source causing the drain to drop to almost GND potential. R316 and R273 then cause the gate of Q1 to go more negative with respect to its source, turning it on.

So basically, it's a solid state on/off switch to the "VCC12 SW" line.

Brian.
I guess, Q1 is an enhancement mode device and Q4 is depletion mode device, right ?
 
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stenzer

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Hi,


if the gate-voltage of Q4 is HIGH (to keep it simple), than it is conductive. If Q4 is conductive, a current is flowing across R316 & R273 towards ground and the gate potential of Q1 is lower than its source potential (--> negative V_GS) and Q1 is turned on. This is usually done if a the control voltage i.e. GPIO HIGH level voltage of a MCU (e.g. 3.3 V or 5 V) is lower than the voltage which should be controled, here 12 V. So here I'm curious where the additional line from MASTER_SW_12V goes to (leaving the screenshot in on the bottom left).

But how about Q1 FDS6681Z, any reason for more than one pin for drain and source ? is that because of current ?
The schematic mentioned a power rating of 2.5 W for Q1, so this one is used for sure to allow a high current flow across it. The number of pins depend on the power rating as well as package of the transistot. For example, a "larger" D-Pak package can handle a "high" power and provides only one (large) drain pin, where a "smaller" SOT-6 package might provide 3 drain pins.

BR
 

joniengr

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Now I have looked at the datasheet of Q4 BSS138 which is N channel enhancement mode MOSFET that will conduct (or work as close switch) when Vgs is more than 1.7 V and will not conduct (or work as open switch) when the voltage is below 1.7 V. I don't know why it's symbol in the schematic look like a depletion mode MOSFET but in the datasheet it's fine having symbol of N channel enhancement mode.

The transistor Q1 FDS6681Z is also enhancement mode MOSFET but p channel that will conduct (or work as close switch) when the voltage Vgs is below –1.8 V and will not conduct (or work as open switch) when the voltage is above -1.8 V.

But coming back to the main question, what is the purpose of introducing these two MOSFETs just after the main supply J15 connector VCC12_P and the physical switch SW1. Protection of other components on the FPGA development board or some other.

The schematic is from Kintex® UltraScale™ FPGA KCU105 Evaluation Kit.
 

betwixt

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Because the MOSFET switch is rated to a maximum of 20A but the switch maybe only a few mA. If the switch alone was used it would have to be physically large. There is also something off the bottom of your schematic which might also control the switch circuit but only capable of small currents.

There are more pins on the package for the source and drain to reduce the internal resistance. All the source pins and all the drain pins are internally linked and connected to the same MOSFET. I expect the reason for drawing the schematic that way is just so all the pin numbers can be shown.

Brian.
 

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Because the MOSFET switch is rated to a maximum of 20A but the switch maybe only a few mA. If the switch alone was used it would have to be physically large. There is also something off the bottom of your schematic which might also control the switch circuit but only capable of small currents.

There are more pins on the package for the source and drain to reduce the internal resistance. All the source pins and all the drain pins are internally linked and connected to the same MOSFET. I expect the reason for drawing the schematic that way is just so all the pin numbers can be shown.

Brian.
Do you mean that physical switch SW1 can only support few mA.
 

betwixt

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The switch rating seems to be about 100mA at 12V, the data sheet I found is rather vague about specifications. It certainly isn't a high power switch and in your application it may also have to carry surge currents if used directly. We can't tell without a full schematic but maybe something else also drives the "MASTER SW 12C" signal that has even lower current capability than the physical switch.

Brian.
 

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