all my cpld outputs are inverted

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ahz571

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i am using webpack 7.1 on the xc9572 cpld . my problem is that whenever i use a "and-gate", its output is as if i am using a "nand gate" (inverted output). did anyone encoutered this problem before?
 

The Xilinx Answer Database is very helpful:
**broken link removed**
 

i am working on the same cpld XC9572 PC44 configuration. i just implemented a decoder so as to check the device and encountered the same problem but when i used the PC84 model, no problems. so use PC84 if you have the resources to do so.
 

ritesh1985 said:
i am working on the same cpld XC9572 PC44 configuration. i just implemented a decoder so as to check the device and encountered the same problem but when i used the PC84 model, no problems. so use PC84 if you have the resources to do so.
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you have to install sp for webpack 7.1.
 

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