fpga dff
Some Xilinx FPGAs also provide special dual data rate (DDR) flops in the IOBs. They have two clocks.
If your design is synchronous and uses only one clock, then maybe all you need is a clock PERIOD constraint. Then your software will automatically place and route the logic to satisfy the setup and hold requirements of all the flops (or it may complain that it can't meet your constraints). For more complex designs and for critical I/O timing, you may need additional timing constraints.
Your timing diagram shows DATA changing simultaneously with CLK. Beware of possible setup/hold violations.