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alias on variable in VHDL

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Full Member level 5
Nov 19, 2004
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vhdl alias

is it possible to use an alias declared from a variable?

variable myvar : std_logic_vector(8 downto 0);
alias mybit : std_logic is myvar (5) ;

alias vhdl

Formal Definition:

An alternate name for an existing named entity. 
Complete description: Language Reference Manual §4.3.3.

Simplified Syntax:

alias alias_name : alias_type is object_name;


The alias declares an alternative name for any existing object: signal, variable, constant or file. It can also be used for "non-objects": virtually everything, which was previously declared, except for labels, loop parameters, and generate parameters.
Alias does not define a new object. It is just a specific name assigned to some existing object.
Aliases are prevalently used to assign specific names to slices of vectors in order to improve readability of the specification (see example 1). When an alias denotes a slice of an object and no subtype indication is given then the subtype of the object is viewed as if it was of the subtype specified by the slice. 

If the alias refers to some other object than a slice and no subtype indication is supported then the object is viewed in the same way as it was declared.
When a subtype indication is supported then the object is viewed as if it were of the subtype specified. In case of arrays, the subtype indication can be of opposite direction than the original object (example 2).
Subtype indication is allowed only for object alias declarations. 
A reference to an alias is implicitly a reference to the object denoted by the alias (example 3).

If an alias denotes a subprogram (including an operator) or enumeration literal then a signature (matching the parameter and result type) is required (example 4). See signature for details.


Example 1
signal Instruction : Bit_Vector(15 downto 0);
alias OpCode : Bit_Vector(3 downto 0) is Instruction(15 downto 12);
alias Source : Bit_Vector(1 downto 0) is Instruction(11 downto 10);
alias Destin : Bit_Vector(1 downto 0) is Instruction(9 downto 8);
alias ImmDat : Bit_Vector(7 downto 0) is Instruction(7 downto 0);

The four aliases in the example above denote four elements of an instruction: operation code, source code, destination code and immediate data supported for some operations. Note that in all declarations the number of bits in the subtype indication and the subtype of the original object match.

Example 2
signal DataBus : Bit_Vector(31 downto 0);
alias FirstNibble : Bit_Vector(0 to 3) is 	DataBus(31 downto 28);

DataBus and FirstNibble have opposite directions. A reference to FirstNibble(0 to 1) is equivalent to a reference to DataBus(31 downto 30).

Example 3
signal Instruction : Bit_Vector(15 downto 0);
alias OpCode : Bit_Vector(3 downto 0) is Instruction(15 downto 12);
. . .
if Opcode = "0101"   -- equivalent to if Instruction(15 downto 12) = 	"0101"
    . . .

Both conditions are exactly the same, but the one where alias is used is more readable.

Important notes:

·	VHDL Language Reference Manual uses the name 'entity' to denote a language unit, i.e. object, parameter etc. It is completely different idea than a design entity. 

·	Many synthesis tools do not support aliases.
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