Algorithm to Hardware

[jefflieu]

Hi guys,
Could some ASIC experts share the flow of implementation of certain algorithm (comm algo or DSP algo for example) ? How do you partition and schedule the algorithm so that you can describe in VHDL?
What are the tools out there do you use (I'm still an industry virgin in Uni ) ... ?
Thanks a lot,
Jeff

 

[nand_gates]

Unfortunately, no one can be told what the Matrix is. You have to see it for yourself.
There are books they teach you Verilog & VHDL but unfortunately there are no book
which talks about algorithm to hardware implementation.
The answer is out there, Neo, and it's looking for you, and it will find you if you want it to.

 

[jefflieu]

You mean that's like art? You need to "synthesize a solution" on case by case basis, relying on your experiences? I just wish to know typical works carried out when a project is defined.
I've implemented control intensive hardware block but this time, I find it weird and uncomfortable to implement a computing intensive algorithm with all the scheduling, partitioning. Just wondering how people do it.
Thanks ,
Jeff

 

[nand_gates]

Yes you are correct! Its like solving a big problem. Unless you start solving it
you wont get the answer.

 

[jefflieu]

I see ...
Thanks ...