How do you divide an 8 bit number by a 4 bit number in Spartan 3 FPGA. Division is not synthesizable in spartan 3.
Added after 1 hours 27 minutes:
I've found the algorithm but i'm not sure how to code it in verilog. here is the alg
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First version of division algorithm and hardware
This is very similar to what we do with pencil and paper. Four registers and a 64-bit ALU are needed. The initial values are as follows: The upper 32 bits (Dh) of the 64-bit register D contains the 32-bit divisor; the lower 32 bits are zero. The 64-bit remainder register R contains the dividend (the upper half is zero). Q, the quotient, contains zero. Here is the division algorithm
Repeat 32 times:
1. Divisor shift right 1 bit, D = D >> 1.
2. Subtract D from R, R = R - D.
3. Quotient shift up, Q = Q << 1; If(R>=0) Q0 = 1, else R = R + D.
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Here's my code
Division is synthesizable in Spartan-3, but it's not synthesizable by the ISE 8.1 Verilog compiler.
What kib means, instead of re-inventing the wheel, you can launch CORE Generator (it's included with your ISE software), look under "Math Functions", and you'll see "Dividers" and then "Divider Generator". Use it to create a division module that you can drop into your HDL project.