Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Algorithm for 8bit/4bit division in spartan 3 FPGA?

Status
Not open for further replies.

david90

Advanced Member level 1
Joined
May 5, 2004
Messages
423
Helped
9
Reputation
18
Reaction score
4
Trophy points
1,298
Activity points
3,610
fpga division

How do you divide an 8 bit number by a 4 bit number in Spartan 3 FPGA. Division is not synthesizable in spartan 3.

Added after 1 hours 27 minutes:

I've found the algorithm but i'm not sure how to code it in verilog. here is the alg
==============
First version of division algorithm and hardware

This is very similar to what we do with pencil and paper. Four registers and a 64-bit ALU are needed. The initial values are as follows: The upper 32 bits (Dh) of the 64-bit register D contains the 32-bit divisor; the lower 32 bits are zero. The 64-bit remainder register R contains the dividend (the upper half is zero). Q, the quotient, contains zero. Here is the division algorithm

Repeat 32 times:

1. Divisor shift right 1 bit, D = D >> 1.
2. Subtract D from R, R = R - D.
3. Quotient shift up, Q = Q << 1; If(R>=0) Q0 = 1, else R = R + D.
============
Here's my code
Code:
module division(clock, divisor, dividend,quotient,remander);
input clock;
input [3:0] divisor;
input [7:0] dividend;

output [3:0]quotient;
output [3:0]remander;

reg [3:0]quotient;
reg [3:0]remander;
reg [7:0]temp;



always@(posedge clock)
begin

temp<=divisor<<4;

quotient=dividend-(temp>>1)
quotient<=quotient<<1;

if (R>=0) 
else 
quotient=dividend+(temp>>1)
end


endmodule
I don't think it is correct though. I'm just confuse about squential logic.

Added after 1 minutes:

I understand the algorithm but I don't know how to code it in verilog sequential logic
 

kib

Advanced Member level 4
Joined
Mar 27, 2003
Messages
111
Helped
10
Reputation
22
Reaction score
2
Trophy points
1,298
Location
Bangalore, India
Activity points
614
fpga division algorithm

use coregen of xilinx ise software to generate a divider
 

echo47

Advanced Member level 5
Joined
Apr 7, 2002
Messages
3,942
Helped
636
Reputation
1,270
Reaction score
88
Trophy points
1,328
Location
USA
Activity points
33,183
division spartan 3

Division is synthesizable in Spartan-3, but it's not synthesizable by the ISE 8.1 Verilog compiler.

What kib means, instead of re-inventing the wheel, you can launch CORE Generator (it's included with your ISE software), look under "Math Functions", and you'll see "Dividers" and then "Divider Generator". Use it to create a division module that you can drop into your HDL project.
 

david90

Advanced Member level 1
Joined
May 5, 2004
Messages
423
Helped
9
Reputation
18
Reaction score
4
Trophy points
1,298
Activity points
3,610
division fpga

oh. Ok. But if I want to make my own module. I just want to learn how.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top