AHB/AXI narrow transfers

[novicevlsi]

beat burst axi

HI

kindly help me out......

In AHB/AXI protocols if the size of transfers is less than the bus width (narrow transfers), for example , if it is 1byte transfer on a 32 bit bus and offset address is 1 , transfer is on second byte lane (AHB). (Little Endian)

similarly for 32 bit transfer on a 64 bit bus trasfer starts on 32-63 bits (from 5-8 byte lanes in AXI) . (little Endian)

pleae refer AHB & AXI for more specific description.

i want to know the reason for these specific Byte Lanes specification.

please explain for Burst cases . Also what about the Alignment ?

when does this narrow transfer case arise....?


thank you so much.........

 

[sree205]

ahb narrow transfer

One possible scenario where this might be used is in a bridge where the other side of the bridge might have lesser data bus width.

 

[novicevlsi]

ahb unaligned transfer

yeah, but what's the reason for those byte enables

 

[sree205]

byte enables are used to send only the relevant information.

lets assume that we have a 1byte data width on the other side of the bridge, and a 2byte data width on the axi side of the bridge, with the bridge using a single clock.

Now, the bridge should be informed about which byte of information should go to the other side,since the other side can only support one byte of data. for that purpose, we use byte enable.

alternative would be to use a fifo and a read clock twice as fast as the axi write clock, but with no phase dif ference(hope i'm right).

 

[eeeraghu]

if a 4 beat burst of 8-bit data is transfered on 32-bit address bus then consider the following
1st transfer
data[7:0] = data;
2nd transfer
data[15:0] = data;
3rd
data[23:16] = data;
and final
data[31:24] = data;

this kind of transfer is used because to utilize the bandwidth of the data,
i.e if the recieving end device has a latency to pick the previous transfer data, it can pick both the current transfer and previous transfer in one cycle.
i.e recieving end data [15:0] = {data1, data2};

thanks

 

[novicevlsi]

the figure has gone alinement!!!

please refer the attached doc.

 

[novicevlsi]

Please refer AMBA AXI v.1


Chapter 10 on unaligned transfers

In Figure 10-1




The start address is given as 0x01 and transfer size is 32 bit. If the data were to be 0xDDCCBBAA, then what is 0x01 corresponding to. Is it byte AA or BB. If it is AA then DD goes to address 0x4 which is not part of first transfer.


If it corresponds to BB , then AA will be written to 0x00 address. But its given in protocol that “The shaded cells indicate bytes that are not transferred, based on the address and control information”.




Here also , if the data were to be 0xDDCCBBAA, then 0x07 corresponds to which bye, DD or AA?

 

[sree205]

going by the AXI specification, each row in the figures represent a transfer. that means, in the first transfer, only 24 bits are transferred, and the first data AA is ignored.

second picture of fig.10.1 shows a burst length of 4 and the total data sent is 120 bits.

Correct me if i'm wrong.