adxl 345 accelerometer code for vhdl

[ukoc]

hi guys,
im working on altera de0 nano cyclone iv. There is a code written with verilog for adxl 345 sensor. I m trying to write same code with vhdl. I' m using spi 3 wire. After sending data format and power control datas i cant recieve x value

here is my code :

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.all;
 
entity clk_yapan is
  port (
  led:inout std_logic_vector(7 downto 0);
    clk_50Mhz : in  std_logic;
      clkMhz : inout  std_logic;
    rst       : in  std_logic;
    clk_2Hz   : out std_logic;
     clk_4Hz   : out std_logic;
         sclk   : out std_logic;
     G_SENSOR_CS_N: out  STD_LOGIC;
                    I2C_SCLK   : out STD_LOGIC;
                    I2C_SDAT    : inout STD_LOGIC;
                    sdat : inout STD_LOGIC;
                    G_SENSOR_INT : in  STD_LOGIC);
     
end clk_yapan ;
 
architecture Behavioral of clk_yapan  is
 
component pll is
port (
inclk0 : IN STD_LOGIC := '0';
c0      : OUT STD_LOGIC );
END COMponent;
 
 
alias y1: std_logic is led(0);
 
 
   constant period:integer:=75;
        CONstant gercekperiod: integer:=1000;--409950
        constant clkperiod:integer:=25;
signal clkcount :integer range 0 to 50000000 :=0;
signal artis,sayac,sayac1,sayac2,kontrol,KONTROL1,artis1:integer:=0;
     signal pwm_reg,pwm_next:std_logic;
  signal prescaler, prescaler1 : unsigned(23 downto 0);
  signal clk_2Hz_i , clk_4Hz_i: std_logic;
   signal tick,tick1,tick2,tick3:std_logic;
     signal counter,counter_next,counter1,counter_next1,counter2,counter_next2:integer:=0;  
  signal w : integer range 0 to 127 := 0 ;
begin
 u0:
 pll    
      port map(
        inclk0 =>clk_50Mhz,
        c0 => clkMhz        );
 
  gen_clk : process (clk_50Mhz, tick,tick1)
  
  begin  -- process gen_clk
  IF TICK = '1' and tick1 = '0' THEN
    if rising_edge(clk_50Mhz) then   -- rising clock edge
      
        clk_2Hz_i   <= clkMhz;
     
      end if;
    
     ELSE 
      clk_2Hz_i   <= '1';
      END IF;
  end process gen_clk;
 
clk_2Hz <= clk_2Hz_i;
 
i2c_SDAT<=sdat;
 
 
tick2<= '1' when counter2 < 3 else
                    '0';
 
 
tick1<= '1' when counter1 <28 else
                    '0';
                          
counter_next2<= 0 when counter2 = gercekperiod else
                           counter1+1;
counter_next1<= 0 when counter1 = gercekperiod else
                           counter1+1;
counter_next<= 0 when counter = period else
                           counter+1;                
tick<= '1' when counter1< 425  else
             '0';                
     
process(clk_50Mhz,tick) 
        begin
            
              if tick='1' then
                 G_SENSOR_CS_N<= '0';
                      else 
                 G_SENSOR_CS_N<= '1';                 
            end if;                            
      end process;
  process(clk_50Mhz)
              begin
                  
                  if clk_50Mhz='1' and clk_50Mhz'event then
                         
                         counter<=counter_next;
                                 counter1<=counter_next1;
                        counter2<= counter_next2;
                   end if;
             end process;
                 
 
                 
                 
process(tick,clk_50Mhz,CLKMhz) 
 
  begin
 
IF Tick = '1' AND TICK2 = '0' then
 
 
 
if  rising_edge(clkMHZ) then
CASE W IS
--Initial
WHEN 0 =>  sdat <= '0'; w <= 1;--0
--Start
WHEN 1 =>  sdat <= '0'; w <= 2; --1
WHEN 2 =>  sdat <= '1'; w <= 3;
--Slave add
WHEN 3 =>  sdat <= '1'; w <= 4;
WHEN 4 =>  sdat <= '0'; w <= 5;
WHEN 5 => sdat <= '0'; w <= 6;
WHEN 6 => sdat <='0' ; w <= 7;
WHEN 7 => sdat <='1' ; w <= 8;
WHEN 8 => sdat <='0' ; w <= 9;
WHEN 9 => sdat <='0' ; w <= 10;
WHEN 10 => sdat <='0' ; w <= 11;
WHEN 11 => sdat <='0' ; w <= 12;
WHEN 12 => sdat <='1' ; w <= 13;
WHEN 13 => sdat <='0' ; w <= 14;
WHEN 14=> sdat <='1' ; w <= 15;
WHEN 15 => sdat <='1' ; w <= 16;
WHEN 16 => sdat <='0' ; w <= 17;
WHEN 17 => sdat <='0' ; w <= 18;
WHEN 18 => sdat <='1' ; w <= 19;
WHEN 19 => sdat <='0' ; w <= 20;
WHEN 20 => sdat <='1' ; w <= 21;
WHEN 21 => sdat <='1' ; w <= 22;
WHEN 22 => sdat <='0' ; w <= 23;
WHEN 23 => sdat <='1' ; w <= 24;
WHEN 24 => sdat <='0' ; w <= 25;
WHEN 25 => sdat <='0' ; w <= 26;
WHEN 26 => sdat <='0' ; w <= 27;
WHEN 27 => sdat <='0' ; w <= 28;
WHEN 28 => sdat <='1' ; w <= 29;
WHEN 29 => sdat <='0' ; w <= 30;
WHEN 30 => sdat <='0' ; w <= 31;
WHEN 31 => sdat <='0' ; w <= 32;
WHEN 32 => sdat <='0' ; w <= 33;
WHEN 33 => sdat <='1' ; w <= 34;
WHEN 34 => sdat <='0' ; w <= 35;
WHEN 35 => sdat <='1' ; w <= 36;
WHEN 36 => sdat <='1' ; w <= 37;
WHEN 37 => sdat <='0' ; w <= 38;
WHEN 38 => sdat <='0' ; w <= 39;
WHEN 39 => sdat <='0' ; w <= 40;
WHEN 40 => sdat <='0' ; w <= 41;
WHEN 41 => sdat <='1' ; w <= 42;
WHEN 42 => sdat <='1' ; w <= 43;
WHEN 43 => sdat <='0' ; w <= 44;
WHEN 44 => sdat <='0' ; w <= 45;
WHEN 45 => sdat <='0' ; w <= 46;
WHEN 46 => sdat <='0' ; w <= 47;
WHEN 47 => sdat <='0' ; w <= 48;
WHEN 48 => sdat <='1' ; w <= 49;
WHEN 49 => sdat <='1' ; w <= 50;
WHEN 50 => sdat <='1' ; w <= 51;
WHEN 51 => sdat <='0' ; w <= 52;
WHEN 52 => sdat <='1' ; w <= 53;
WHEN 53 => sdat <='1' ; w <= 54;
WHEN 54 => sdat <='0' ; w <= 55;
WHEN 55 => sdat <='0' ; w <= 56;
WHEN 56 => sdat <='1' ; w <= 57;
WHEN 57 => sdat <='1' ; w <= 58;
when 58 => sdat <= null; w<= 59;
 
when others =>w<=58;
end case;
end if; 
else 
sdat <= '1';
end if;
        
      end process;                       
 
end Behavioral;

---

clk_2hz is sclk and sdat is SDIO i used 2 mhz clock for sensor.

thank you and sorry for my bad english :razz:

 

[andre_luis]

You code is very confusing, seemingly having garbage you left form other program ( e.g PWM signal ). You don't manage reset signal (rst) anywhere, as well I2C_SCLK isn't used. Do you really expect to see it working ?

 

[ads-ee]

If the code you had in Verilog was architecturally the same as this VHDL version, you should find a better Verilog or VHDL example of SPI code. This architecture is not at all good.

I hope you are aware that SPI is a SERIAL protocol and shift registers are used when doing things serially...

This is a counter and an enormous mulitplexer combined.

---

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
if  rising_edge(clkMHZ) then
CASE W IS
--Initial
WHEN 0 =>  sdat <= '0'; w <= 1;--0
--Start
WHEN 1 =>  sdat <= '0'; w <= 2; --1
WHEN 2 =>  sdat <= '1'; w <= 3;
--
-- lines and lines of multiplexing deleted to reduce the length of code
--
when 58 => sdat <= null; w<= 59;
 
when others =>w<=58;
end case;
end if; 
else 
sdat <= '1';
end if;

---

Based on the code above w behaves as a counter, so why isn't this written as a counter? The signal sdat is a serial output, so why is it coded using a multiplexer? It's pretty obvious you don't understand that VHDL stands for VHSIC Hardware Description Language. The key being this language is supposed to describe hardware, and the hardware you are describing is more like a C program than what you would design in hardware. You also have a bunch of problems with the contents of your process sensitivity lists. You have signals that don't belong in the list ones that should (based on the code you wrote) but aren't in the list.

Besides that, SPI even 3-wire uses the names MISO (master in slave out), MOSI (master out slave in) and SCLK (SPI clock) for the names. Notice that there are two lines a transmit (MO..) and a receive (MI..). You have it defined as a bi-directional, which is not going to work.

You should sit down and decide what the architecture of your hardware design is before writing any VHDL code. Right now this is a big mess.

- - - Updated - - -

update:
Actually is this really SPI or I2C as I just noticed that you are assigning sdat to i2c_sdat. Well SPI is an entirely different protocol from I2C, so why did you say you are using SPI 3-wire in your description of the problem? If it is really I2C you never assign Z to sdat to disable driving the signal when the signal is supposed to be receiving serial data.