Never used , but look good but too slow...
https://www.microchip.com/ParamChartSearch/chart.aspx?branchID=11022&mid=10&lang=en&pageId=79
Have you considered many slow ADC’s using analog muxed S&H and muxed data out on I2C? or using a 4 to 5 decade AGC to amplify the signal to flat line and measure the AGC control like RSSI does with 1 dB resolution on WiFI over a 100 dB range with excellent accuracy? ( in concept not same IC’s
Keep in mind LF contributions of E fields at line frequency. See some much CM signal you get on a 10M probe while grabbing a bare loose long wire to the probe without touching ground. If you get >75 Vp then you know you need more than 120 dB CMRR on your inputs before amplification. I'm suggest to verify your SNR input after gain before you tackle the ADC issues. The same is true for AM broadcast noise and other RF impulse (ESD) transients. You may need active shielding with CM chokes rather than conventional STP cables with passive balancing, much like EMG amplifiers.
A matched filter on the front is ideal (matched to spectrum of signal) as long as group delay does not cause skirt detection issues and lag in sweep response of sensor. (use Gaussian LPF’s) .
The most effective design method I know, is to specify a noise margin required and budget a limit for each and every possible noise source in order to realize a perfect solution. (Anything that meets spec is perfect, but without specs for each noise source, how will you know or have a criteria when it comes to DVT or design validation testing) This includes radiated, and conducted from all spectral potential sources including DC to RF to optical to gamma if applicable) with pulse, continuous and modulated sources of noise and there are a gamut of industry standard tests for ingress noise test verification. I’ve done this on many products, including magnetic HDD’s in the 80’s . A full DVT often is about 30 environmental tests to verify each and every design spec to measure margin to interference or error from each source. climatic, mechanical, electrical etc. Even microphonic ceramic caps, cables, poor solder joints can induce intermittent problems that are best tested by making specs and verify during DVT. I often used a hand vibrator to look for fragility problems on cards with cold spray and heat guns for thermal instability on system performance or injected pseudorandom noise on signals to determine the margin of noise. Solder is often the biggest prototype defect from process design, but design flaws are under your control after you define the specs to define any parameter or even unknowns.
ADC’s are also prone to horrible monotonic errors from noise. One only has to view a 256 grey scale pallete on their video card and display and look for major patterns transitions to see the effects of digital noise shifting the Vreference in the DAC and causing errors in monotonicity on all computer cards and LCD displays. (some worse than others) After all the DAC is a critical part in the ADC but the errors usually come from ground shift of logic current induce voltages in fhe analog ground. To explain simply it’s when xxxx0111xxxx goes to xxxx1000xxx and the digital ground shift noise skips that voltage level or causes monotonicity errors. I have seen this on too many systems to know one can not assume the chip specs will apply to whole card or system. My 1st experience was discovering flaws in a Burr Brown 12 bit flash ABC hybrid made to Mil Std 883 quality levels in late 70’s then Motorola CPU ADC’s and now LCD DAC’s in video monitors using “DPT.exe” free tool with video test patterns for windows.
For monotonic errors, anything but C0G ceramic or metal film caps must be avoided in the Signal S&H to prevent hysteresis and microphonic effects. The same applies to capactive touch screen reference caps.