I'm doing some research on choosing another simulation tool than NCVerilog. And SystemVerilog seems to have some stronger features than Verilog ... Anyone here used to use both of them can share some experiences here ??? SV is deserved to purchase ???
SV is not a simulator,it is an advanced feature of Verilog.
Which can be used for System level design,Synthesisable RTL design and
can be used for Verification to interface C to ur Verilog or SV code.
Verilog95 ---> Verilog 2001 ----> SystemVerilog.
So any simulator which u are working earlier(Modelsim or NcVerilog or VCS)
will be ok,provided u use the latest versions of those simulators.
Only latest versions supports SV.
SystemVerilog is an language which is most usually used for verification today.
Some syntax of SystemVerilog can't used when use ncverilog simulator.
VCS is another good choise when choose simulator