yousif
Member level 1
In TI ADS1258 ADC datasheet in (Figure 56. Start Condition to First Data) it is said that to allow fully-settled data to occur at the first data read, a number of clock cycles must be delayed.
This delay for fixed-channel conversion is at least 802 clock cycles which is very long period (~= 52 mS) and presents big conversion latency when switching from one channel to another.
Am I understanding that well or there is something wrong ?
Please help !
This delay for fixed-channel conversion is at least 802 clock cycles which is very long period (~= 52 mS) and presents big conversion latency when switching from one channel to another.
Am I understanding that well or there is something wrong ?
Please help !
